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Nelson Chu
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Refer mapping symbol into R_RISCV_RELAX for rvc/norvc relaxations.
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riscv-elf.adoc

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@@ -201,6 +201,7 @@ below.
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[[EF_RISCV_RVC]]
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EF_RISCV_RVC (0x0001)::: This bit is set when the binary targets the C ABI,
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which allows instructions to be aligned to 16-bit boundaries (the base RV32
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and RV64 ISAs only allow 32-bit instruction alignment). When linking
@@ -430,7 +431,7 @@ Description:: Additional information about the relocation
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<| S + A
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.2+| 47-50 .2+| *Reserved* .2+| - | .2+| Reserved for future standard use
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<|
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.2+| 51 .2+| RELAX .2+| Static | .2+| Instruction can be relaxed, paired with a normal relocation at the same address
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.2+| 51 .2+| RELAX .2+| Static | .2+| Instruction can be relaxed, paired with a normal relocation at the same address. This relocation might point to an optional dummy mapping symbol, indicating which extension is permitted for use during the linker relaxation process.
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<|
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.2+| 52 .2+| SUB6 .2+| Static | _word6_ .2+| Local label subtraction
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<| V - S - A
@@ -1622,6 +1623,37 @@ instructions. It is recommended to initialize `jvt` CSR immediately after
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csrw jvt, a0
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----
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=== Compressed and Non-compressed Relaxations in the Same Object
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Linker used to enables and disables the compressed relaxations by checking the
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[[EF_RISCV_RVC]] of each intput object. Since [[EF_RISCV_RVC]] is an
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object-level tag, it cannot handle the case that if `.option arch, +c` and
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`.option arch, -c` are in the same object. Therefore, encode the mapping symbols
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into each R_RISCV_RELAX can resolve the problem.
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Example::
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+
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--
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Relaxation candidate:
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[,asm]
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----
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.option arch, rv32i
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auipc ra, 0 # R_RISCV_CALL_PLT (symbol), R_RISCV_RELAX ($xrv32i)
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jalr ra, ra, 0
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.option arch, +c
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auipc ra, 0 # R_RISCV_CALL_PLT (symbol), R_RISCV_RELAX ($xrv32ic)
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jalr ra, ra, 0
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----
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Relaxation result:
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[,asm]
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----
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jal ra, 0 # R_RISCV_JAL (symbol)
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c.jal ra, <offset-between-pc-and-symbol>
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----
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--
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[bibliography]
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== References
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