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Merge pull request #168 from ebahapo/patch-3
Fix relocations fields
2 parents a1ec2f7 + 069290b commit 2bcc560

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riscv-elf.md

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@@ -542,8 +542,8 @@ Enum | ELF Reloc Type | Description | Field | C
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11 | R_RISCV_TLS_TPREL64 | Runtime TLS relocation | _word64_ | S + A + TLSOFFSET
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16 | R_RISCV_BRANCH | PC-relative branch | _B-Type_ | S + A - P
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17 | R_RISCV_JAL | PC-relative jump | _J-Type_ | S + A - P
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18 | R_RISCV_CALL | PC-relative call | _J-Type_ | S + A - P | Macros `call`, `tail`
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19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _J-Type_ | S + A - P | Macros `call`, `tail` (PIC)
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18 | R_RISCV_CALL | PC-relative call | _U+J-Type_ | S + A - P | Macros `call`, `tail`
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19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _U+J-Type_ | S + A - P | Macros `call`, `tail` (PIC)
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20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A - P | `%got_pcrel_hi(symbol)`
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21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie`
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22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd`
@@ -633,6 +633,7 @@ _I-Type_ | Specifies a field as the immediate field in an I-type instruction
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_S-Type_ | Specifies a field as the immediate field in an S-type instruction
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_U-Type_ | Specifies a field as the immediate field in an U-type instruction
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_J-Type_ | Specifies a field as the immediate field in a J-type instruction
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_U+J-Type_ | Specifies a field as the immediate fields in a U-type and J-type instruction pair
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### Constants
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@@ -779,7 +780,7 @@ and when `-fpic` is enabled it expands to:
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### PC-Relative Jumps and Branches
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Unconditional jump (UJ-Type) instructions have a `R_RISCV_JAL` relocation
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Unconditional jump (U+J-Type) instructions have a `R_RISCV_JAL` relocation
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that can represent an even signed 21-bit offset (-1MiB to +1MiB-2).
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Branch (SB-Type) instructions have a `R_RISCV_BRANCH` relocation that

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