Add initial specification for Big Endian

Author: djtodoro

introduction.adoc

@@ -58,7 +58,29 @@ This specification uses the following terms and abbreviations:
 | RV64ILP32Q        | Draft
 |===
 
-NOTE: ABI for big-endian is *NOT* included in this specification, we intend to
-define that in future version of this specification.
+=== Big-endian ABI Status
+
+[width=80%]
+|===
+| ABI Name          | Status
+
+| ILP32 (BE)        | Draft
+| ILP32F (BE)       | Draft
+| ILP32D (BE)       | Draft
+| ILP32E (BE)       | Draft
+| LP64 (BE)         | Draft
+| LP64F (BE)        | Draft
+| LP64D (BE)        | Draft
+| LP64Q (BE)        | Draft
+| RV64ILP32 (BE)    | Draft
+| RV64ILP32F (BE)   | Draft
+| RV64ILP32D (BE)   | Draft
+| RV64ILP32Q (BE)   | Draft
+|===
+
+NOTE: This specification now includes preliminary support for big-endian ABIs.
+Big-endian support has been implemented in GNU GCC and LLVM/Clang toolchains.
+The big-endian variants follow the same calling conventions as their
+little-endian counterparts, with only the data byte ordering differing.
 
 :sectnums:

riscv-cc.adoc

@@ -167,8 +167,10 @@ callee-saved registers must be restored to what was set on entry, and the
 contents of any fixed registers like `gp` and `tp` never change.
 
 
-NOTE: Calling convention for big-endian is *NOT* included in this specification
-yet, we intend to define that in future version of this specification.
+NOTE: Big-endian calling conventions follow the same rules as little-endian
+calling conventions. The only difference is in the byte ordering of multi-byte
+values in memory and registers. Register usage, argument passing, and return
+value conventions remain the same.
 
 [#integer-cc]
 === Integer Calling Convention

riscv-elf.adoc

@@ -236,6 +236,48 @@ type-name = identifier-nondigit *identifier-char
 identifier-nondigit = ALPHA / "_"
 identifier-char = identifier-nondigit / "_"
 ----
+
+== Data Representation
+
+The data representation for RISC-V follows the conventions of the target endianness.
+RISC-V supports both little-endian and big-endian byte ordering.
+
+=== Byte Ordering
+
+RISC-V implementations can support either little-endian or big-endian byte ordering:
+
+* **Little-endian**: The least significant byte is stored at the lowest memory address.
+  This is the default and most common byte ordering for RISC-V.
+* **Big-endian**: The most significant byte is stored at the lowest memory address.
+
+The endianness is fixed at the system level and cannot be changed dynamically.
+All data types follow the byte ordering of the target system.
+
+IMPORTANT: RISC-V instructions are always stored in little-endian format,
+regardless of the data endianness. This means that in big-endian systems,
+data is big-endian but instructions remain little-endian.
+
+=== Relocations and Byte Ordering
+
+When generating big-endian output, the following relocations write their
+data values in big-endian byte order:
+
+* `R_RISCV_32` - 32-bit data relocation
+* `R_RISCV_64` - 64-bit data relocation
+* `R_RISCV_ADD16` - 16-bit label addition
+* `R_RISCV_ADD32` - 32-bit label addition
+* `R_RISCV_ADD64` - 64-bit label addition
+* `R_RISCV_SUB16` - 16-bit label subtraction
+* `R_RISCV_SUB32` - 32-bit label subtraction
+* `R_RISCV_SUB64` - 64-bit label subtraction
+* `R_RISCV_SET16` - 16-bit local label assignment
+* `R_RISCV_SET32` - 32-bit local label assignment
+* `R_RISCV_32_PCREL` - 32-bit PC-relative relocation
+* `R_RISCV_PLT32` - 32-bit relative offset to PLT entry
+
+All other relocations that modify instruction fields continue to use
+little-endian byte order, as RISC-V instructions are always little-endian.
+
 == ELF Object Files
 
 The ELF object file format for RISC-V follows the