We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 2671e51 commit 5675bc5Copy full SHA for 5675bc5
riscv-elf.md
@@ -422,6 +422,7 @@ rules about 2✕XLEN aligned arguments being passed in "aligned" register pairs.
422
and RV64 ISAs only allow 32-bit instruction alignment). When linking
423
objects which specify EF_RISCV_RVC, the linker is permitted to use RVC
424
instructions such as C.JAL in the relaxation process.
425
+ * EF_RISCV_FLOAT_ABI_SOFT (0x0000)
426
* EF_RISCV_FLOAT_ABI_SINGLE (0x0002)
427
* EF_RISCV_FLOAT_ABI_DOUBLE (0x0004)
428
* EF_RISCV_FLOAT_ABI_QUAD (0x0006): These three flags identify the floating
0 commit comments