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Merge pull request #261 from riscv-non-isa/tweaks
Minor grammar and style improvements
2 parents d6a45d5 + ed0b6c2 commit 966a1ac

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riscv-cc.adoc

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@@ -28,8 +28,8 @@ endif::[]
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In the standard ABI, procedures should not modify the integer registers tp and
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gp, because signal handlers may rely upon their values.
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The presence of a frame pointer is optional. If a frame pointer exists
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it must reside in x8 (s0), the register remains callee-saved.
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The presence of a frame pointer is optional. If a frame pointer exists,
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it must reside in x8 (s0); the register remains callee-saved.
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=== Floating-point Register Convention
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@@ -100,7 +100,7 @@ available, the scalar is passed on the stack by value. If exactly one
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register is available, the low-order XLEN bits are passed in the register and
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the high-order XLEN bits are passed on the stack.
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Scalars wider than 2×XLEN are passed by reference and are replaced in the
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Scalars wider than 2×XLEN bits are passed by reference and are replaced in the
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argument list with the address.
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Aggregates whose total size is no more than XLEN bits are passed in
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Arguments passed by reference may be modified by the callee.
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Floating-point reals are passed the same way as aggregates of the same size,
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Floating-point reals are passed the same way as aggregates of the same size;
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complex floating-point numbers are passed the same way as a struct containing
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two floating-point reals. (This constraint changes when the integer calling
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convention is augmented by the hardware floating-point calling convention.)
@@ -219,7 +219,7 @@ A struct containing just one floating-point real is passed as though it were
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a standalone floating-point real.
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A struct containing two floating-point reals is passed in two floating-point
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registers, if neither is more than FLEN bits wide and at least two floating-point
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registers, if neither real is more than FLEN bits wide and at least two floating-point
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argument registers are available. (The registers need not be an aligned pair.)
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Otherwise, it is passed according to the integer calling convention.
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riscv-elf.adoc

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@@ -21,7 +21,7 @@ in the current code model.
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=== Small code model
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The small code model, or `medlow`, allows the code to address the whole RV32
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address space or the lower 2 GiB and highest 2GiB of the RV64 address space
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address space or the lower 2 GiB and highest 2 GiB of the RV64 address space
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(`0xFFFFFFFF7FFFF800` ~ `0xFFFFFFFFFFFFFFFF` and `0x0` ~ `0x000000007FFFF7FF`).
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By using the instructions `lui` and `ld` or `st`, when referring to an object, or
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`addi`, when calculating an address literal, for example,
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--
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e_machine:: Identifies the machine this ELF file targets. Always contains
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EM_RISCV (243) for RISC-V ELF files. We only support RISC-V v2 family ISAs,
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EM_RISCV (243) for RISC-V ELF files. We only support RISC-V v2 family ISAs;
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this support is implicit.
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e_flags:: Describes the format of this ELF file. These flags are used by the
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Enum:: The number of the relocation, encoded in the r_info field
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ELF Reloc Type:: The name of the relocation, omitted the prefix of `R_RISCV_` here.
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ELF Reloc Type:: The name of the relocation, omitting the prefix of `R_RISCV_`.
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Type:: Whether the relocation is a static or runtime relocation:
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+
@@ -523,7 +523,7 @@ The following assembly and relocations show loading an absolute address:
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==== Global Offset Table
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For position independent code in dynamically linked objects, each shared
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object contains a GOT (Global Offset Table) which contains addresses of
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object contains a GOT (Global Offset Table), which contains addresses of
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global symbols (objects and functions) referred to by the dynamically
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linked shared object. The GOT in each shared library is filled in by the
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dynamic linker during program loading, or on the first call to extern functions.
@@ -823,7 +823,7 @@ In the Global Dynamic model, the runtime library provides the `__tls_get_addr` f
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extern void *__tls_get_addr (tls_index *ti);
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----
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where the type tls index are defined as:
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where the type tls_index is defined as:
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[,c]
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----

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