Apply more consistent title case to section titles

Author: jrtc27

riscv-atomic.adoc

@@ -4,7 +4,7 @@ ifeval::["{docname}" == "riscv-atomics"]
 include::prelude.adoc[]
 endif::[]
 
-== RISC-V atomics mappings
+== RISC-V Atomics Mappings
 
 This specifies mappings of C and {Cpp} atomic operations to RISC-V
 machine instructions. Other languages, for example Java, provide similar
@@ -134,7 +134,7 @@ the `lr` and `sc` instructions.
 |===
 
 [discrete]
-=== Meaning of notes in table
+=== Meaning of Notes in Table
 
 1) Depends on a load instruction with an RCsc acquire annotation,
 or a store instruction with an RCsc release annotation. These are currently
@@ -154,7 +154,7 @@ ordering are considered to have a note 3 annotation.
 To remove the note 3 annotation the amocas operation must be prepended with a
 leading fence (`fence rw,rw; amocas.{w\|d}.aqrl`).
 
-== Ztso atomics mappings
+== Ztso Atomics Mappings
 
 This specifies additional mappings of C and {Cpp} atomic operations to RISC-V
 machine instructions.
@@ -219,7 +219,7 @@ We present the mappings as a table in 3 sections, as above.
 |===
 
 [discrete]
-=== Meaning of notes in table
+=== Meaning of Notes in Table
 
 3) Incompatible with the original "Table A.6" mapping. Do not combine these
 mappings with code generated by a compiler using those older mappings.
@@ -234,7 +234,7 @@ leading fence (`fence rw,rw; amocas.{w\|d}`).
 
 6) Requires the Ztso extension.
 
-== Other conventions
+== Other Conventions
 
 It is expected that the RVWMO and Ztso AMO Mappings will be used for atomic
 read-modify-write operations that are directly supported by corresponding AMO

riscv-cc.adoc

@@ -74,7 +74,7 @@ convention. A platform may choose:
 - to use the frame pointer to address a valid frame record at all times, except
   leaf functions, who may elect to forgo creating a frame record.
 
-=== Floating-point Register Convention
+=== Floating-Point Register Convention
 
 .Floating-point register convention
 [cols="1,1,2,2"]
@@ -99,7 +99,7 @@ duration in accordance with C11 section 7.6 "Floating-point environment
 
 === Vector Register Convention
 
-==== Standard calling convention
+==== Standard Calling Convention
 .Standard vector register calling convention
 [%autowidth]
 |===
@@ -126,7 +126,7 @@ NOTE: Application software should normally not write `vstart` explicitly.
 Any procedure that does explicitly write `vstart` to a nonzero value must zero
 `vstart` before either returning or calling another procedure.
 
-==== Calling convention variant
+==== Calling Convention Variant
 .Variant vector register calling convention*
 [%autowidth]
 |===
@@ -266,7 +266,7 @@ No floating-point registers, if present, are preserved across calls. (This
 property changes when the integer calling convention is augmented by the
 hardware floating-point calling convention.)
 
-=== Hardware Floating-point Calling Convention
+=== Hardware Floating-Point Calling Convention
 
 The hardware floating-point calling convention adds eight floating-point
 argument registers, fa0-fa7, the first two of which are also used to return
@@ -556,9 +556,9 @@ document.
 Please refer to the documentation of the RISC-V execution environment interface
 (e.g OS kernel ABI, SBI).
 
-== C/{Cpp} type details
+== C/{Cpp} Type Details
 
-=== C/{Cpp} type sizes and alignments
+=== C/{Cpp} Type Sizes and Alignments
 
 There are two conventions for C/{Cpp} type sizes and alignments.
 
@@ -622,7 +622,7 @@ The alignment of `max_align_t` is 16.
 Structs and unions are aligned to the alignment of their most strictly aligned
 member. The size of any object is a multiple of its alignment.
 
-=== Fixed-length vector
+=== Fixed-Length Vector
 
 Various compilers have support for fixed-length vector types, for example GCC
 and Clang both support declaring a type with `\\__attribute__\((vector_size(N))`,
@@ -634,7 +634,7 @@ alignment requirement of its elemental type.
 The size of the fixed length vector is determined by multiplying the size of its
 elemental type by the total number of elements within the vector.
 
-=== C/{Cpp} type representations
+=== C/{Cpp} Type Representations
 
 `char` is unsigned.
 
@@ -655,7 +655,7 @@ The type `size_t` is defined as `unsigned int` for RV32 and `unsigned long` for
 
 The type `ptrdiff_t` is defined as `int` for RV32 and `long` for RV64.
 
-=== Bit-fields
+=== Bit-Fields
 
 Bit-fields are packed in little-endian fashion. A bit-field that would span the
 alignment boundary of its integer type is padded to begin at the next
@@ -716,7 +716,7 @@ alignment used will be those of a pointer, and the fetched pointer will be used
 as the address of the actual argument. The `va_copy` macro is a single pointer
 copy and the `va_end` macro performs no operation.
 
-=== Vector type sizes and alignments
+=== Vector Type Sizes and Alignments
 
 This section defines the sizes and alignments for the vector types defined in
 the _RISC-V Vector Extension Intrinsic Document_<<rvv-intrinsic-doc>>.
@@ -749,7 +749,7 @@ content may be undefined, both in the register and in memory.
 NOTE: Size must be a positive integer.
 
 [appendix]
-== Linux-specific ABI
+== Linux-Specific ABI
 
 NOTE: This section of the RISC-V calling convention specification only applies
 to Linux-based systems.
@@ -758,7 +758,7 @@ In order to ensure compatibility between different implementations of the C
 library for Linux, we provide some extra definitions which only apply on those
 systems. These are noted in this section.
 
-=== Linux-specific C type sizes and alignments
+=== Linux-Specific C Type Sizes and Alignments
 
 The following definitions apply for all ABIs defined in this document. Here
 there is no differentiation between ILP32 and LP64 ABIs.
@@ -773,7 +773,7 @@ there is no differentiation between ILP32 and LP64 ABIs.
 | wint_t  |  4           |  4
 |===
 
-=== Linux-specific C type representations
+=== Linux-Specific C Type Representations
 
 The following definitions apply for all ABIs defined in this document. Here
 there is no differentiation between ILP32 and LP64 ABIs.

riscv-elf.adoc

@@ -4,7 +4,7 @@ ifeval::["{docname}" == "riscv-elf"]
 include::prelude.adoc[]
 endif::[]
 
-== Code models
+== Code Models
 
 The RISC-V architecture constrains the addressing of positions in the
 address space.  There is no single instruction that can refer to an arbitrary
@@ -18,7 +18,7 @@ However, some code models can't access the whole address space. The linker may
 raise an error if it cannot adjust the instructions to access the target address
 in the current code model.
 
-=== Medium low code model
+=== Medium Low Code Model
 
 The medium low code model, or `medlow`, allows the code to address the whole RV32
 address space or the lower 2 GiB and highest 2 GiB of the RV64 address space
@@ -59,7 +59,7 @@ lui a0, 0x80000 # a0 = 0xffffffff80000000
 addi a0, a0, -0x800 # a0 = a0 + -2048 = 0xFFFFFFFF7FFFF800
 ----
 
-=== Medium any code model
+=== Medium Any Code Model
 
 The medium any code model, or `medany`, allows the code to address the range
 between -2 GiB and +2 GiB from its position.  By using `auipc`
@@ -103,7 +103,7 @@ for that, please use the medium position independent code model below.
 
 NOTE: The address space of RV64ILP32* ABIs is not continuous in the middle.
 
-=== Medium position independent code model
+=== Medium Position Independent Code Model
 
 This model is similar to the medium any code model, but uses the
 <<Global Offset Table,global offset table>> (GOT) for non-local symbol addresses.
@@ -127,7 +127,7 @@ This model is similar to the medium any code model, but uses the
          l[w|d] a0, %pcrel_lo(.Ltmp3)(a0)
 ----
 
-=== Large code model
+=== Large Code Model
 
 The `large` code model allows the code to address the whole RV64 address space.
 Thus, this model is only available for RV64. By putting object addresses
@@ -207,7 +207,7 @@ same way as `std::bfloat16_t`.
 === Name Mangling for Vector Data Types, Vector Mask Types and Vector Tuple Types.
 
 The vector data types and vector mask types, as defined in the section
-<<Vector type sizes and alignments>>, are treated as vendor-extended types in
+<<Vector Type Sizes and Alignments>>, are treated as vendor-extended types in
 the _Itanium {Cpp} ABI_ <<itanium-cxx-abi>>. These mangled name for
 these types is `"u"<len>"__rvv_"<type-name>`. Specifically,
 prefixing the type name with `__rvv_`, which is prefixed by
@@ -339,7 +339,7 @@ and the operating system, and the ABI differences are so significant they
 cannot be done with a .RISCV.attributes tag nor an ELF note, such as using a
 different syscall ABI.
 
-==== Policy for Merge Objects With Different File Headers
+==== Policy for Merge Objects with Different File Headers
 
 This section describe the behavior when the inputs files come with different
 file headers.
@@ -1241,7 +1241,7 @@ In order to improve the compatibility of the tool, the attribute follows below r
 - The tag is optional; If the tool does not recognize this attribute and the tag number
   modulo 128 is greater than or equal to 64 (`(N % 128) >= 64`), the tag can be ignored.
 
-==== Layout of .riscv.attributes section
+==== Layout of .riscv.attributes Section
 
 The attributes section start with a format-version (uint8 = 'A') followed by
 vendor specific sub-section(s). A sub-section starts with sub-section length
@@ -1256,7 +1256,7 @@ A sub-section with name "riscv\0" is mandatory. Vendor specific sub-sections
 are allowed in future. Vendor names starting with "[Aa]non" are reserved for
 non-standard ABI extensions.
 
-==== List of attributes
+==== List of Attributes
 
 .RISC-V attributes
 [cols="4,>2,2,5"]
@@ -1275,7 +1275,7 @@ non-standard ABI extensions.
 | Reserved for non-standard attribute | >= 32768 | -              | -
 |===
 
-==== Detailed attribute description
+==== Detailed Attribute Description
 
 ===== How does this specification describe public attributes?
 
@@ -1647,7 +1647,7 @@ Relaxation result:
 --
 
 [[gp-relax]]
-==== Global-pointer Relaxation
+==== Global-Pointer Relaxation
 
   Target Relocation:: R_RISCV_HI20, R_RISCV_LO12_I, R_RISCV_LO12_S,
   R_RISCV_PCREL_HI20, R_RISCV_PCREL_LO12_I, R_RISCV_PCREL_LO12_S
@@ -1737,7 +1737,7 @@ optimize code size and performance of the symbol accessing.
 
 NOTE: Tag_RISCV_x3_reg_usage is treated as 0 if it is not present.
 
-==== GOT load relaxation
+==== GOT Load Relaxation
 
   Target Relocation:: R_RISCV_GOT_HI20, R_RISCV_PCREL_LO12_I
 
@@ -1811,7 +1811,7 @@ Relaxation result (relative symbol):
 ----
 --
 
-==== Zero-page Relaxation
+==== Zero-Page Relaxation
 
   Target Relocation:: R_RISCV_HI20, R_RISCV_LO12_I, R_RISCV_LO12_S
 
@@ -1880,7 +1880,7 @@ Relaxation result:
 ----
 --
 
-==== Thread-pointer Relaxation
+==== Thread-Pointer Relaxation
 
   Target Relocation:: R_RISCV_TPREL_HI20, R_RISCV_TPREL_ADD,
   R_RISCV_TPREL_LO12_I, R_RISCV_TPREL_LO12_S.

riscv-rtabi.adoc

@@ -1,10 +1,10 @@
 [[riscv-rtabi]]
-= RISC-V Run-time ABI Specification
+= RISC-V Run-Time ABI Specification
 ifeval::["{docname}" == "riscv-rtabi"]
 include::prelude.adoc[]
 endif::[]
 
-== Run-time ABI
+== Run-Time ABI
 
 This document defines the run-time helper function ABI for RISC-V, which
 includes compiler helper functions, but does not cover the language standard