From 4e3bc4b70c3dc6925c4e5a4f4398b41b0024983f Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Wed, 3 Jun 2020 19:45:46 -0500 Subject: [PATCH 01/18] Augment the relocations table Change the relocations table to include the respective calculations and organize the information in specific columns. --- riscv-elf.md | 159 +++++++++++++++++++++++++++++---------------------- 1 file changed, 90 insertions(+), 69 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 5768b359..110a753b 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -469,65 +469,65 @@ Global Offset Table or DWARF meta data. The following table provides details of the RISC-V ELF relocations (instruction specific relocations show the instruction type in the Details column): -Enum | ELF Reloc Type | Description | Details -:--- | :------------------ | :--------------- | :----------- -0 | R_RISCV_NONE | None | -1 | R_RISCV_32 | Runtime relocation | word32 = S + A -2 | R_RISCV_64 | Runtime relocation | word64 = S + A -3 | R_RISCV_RELATIVE | Runtime relocation | word32,64 = B + A -4 | R_RISCV_COPY | Runtime relocation | must be in executable. not allowed in shared library -5 | R_RISCV_JUMP_SLOT | Runtime relocation | word32,64 = S ;handled by PLT unless LD_BIND_NOW -6 | R_RISCV_TLS_DTPMOD32 | TLS relocation | word32 = S->TLSINDEX -7 | R_RISCV_TLS_DTPMOD64 | TLS relocation | word64 = S->TLSINDEX -8 | R_RISCV_TLS_DTPREL32 | TLS relocation | word32 = TLS + S + A - TLS_TP_OFFSET -9 | R_RISCV_TLS_DTPREL64 | TLS relocation | word64 = TLS + S + A - TLS_TP_OFFSET -10 | R_RISCV_TLS_TPREL32 | TLS relocation | word32 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET -11 | R_RISCV_TLS_TPREL64 | TLS relocation | word64 = TLS + S + A + S_TLS_OFFSET - TLS_DTV_OFFSET -16 | R_RISCV_BRANCH | PC-relative branch | (SB-Type) -17 | R_RISCV_JAL | PC-relative jump | (UJ-Type) -18 | R_RISCV_CALL | PC-relative call | MACRO call,tail (auipc+jalr pair) -19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | MACRO call,tail (auipc+jalr pair) PIC -20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | %got_pcrel_hi(symbol) (U-Type) -21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | MACRO la.tls.ie -22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | MACRO la.tls.gd -23 | R_RISCV_PCREL_HI20 | PC-relative reference | %pcrel_hi(symbol) (U-Type) -24 | R_RISCV_PCREL_LO12_I | PC-relative reference | %pcrel_lo(pcrel_hi20_address) (I-Type) -25 | R_RISCV_PCREL_LO12_S | PC-relative reference | %pcrel_lo(pcrel_hi20_address) (S-Type) -26 | R_RISCV_HI20 | Absolute address | %hi(symbol) (U-Type) -27 | R_RISCV_LO12_I | Absolute address | %lo(symbol) (I-Type) -28 | R_RISCV_LO12_S | Absolute address | %lo(symbol) (S-Type) -29 | R_RISCV_TPREL_HI20 | TLS LE thread offset | %tprel_hi(symbol) (U-Type) -30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | %tprel_lo(symbol) (I-Type) -31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | %tprel_lo(symbol) (S-Type) -32 | R_RISCV_TPREL_ADD | TLS LE thread usage | %tprel_add(symbol) -33 | R_RISCV_ADD8 | 8-bit label addition | word8 = old + S + A -34 | R_RISCV_ADD16 | 16-bit label addition | word16 = old + S + A -35 | R_RISCV_ADD32 | 32-bit label addition | word32 = old + S + A -36 | R_RISCV_ADD64 | 64-bit label addition | word64 = old + S + A -37 | R_RISCV_SUB8 | 8-bit label subtraction | word8 = old - S - A -38 | R_RISCV_SUB16 | 16-bit label subtraction | word16 = old - S - A -39 | R_RISCV_SUB32 | 32-bit label subtraction | word32 = old - S - A -40 | R_RISCV_SUB64 | 64-bit label subtraction | word64 = old - S - A -41 | R_RISCV_GNU_VTINHERIT| GNU C++ vtable hierarchy | -42 | R_RISCV_GNU_VTENTRY | GNU C++ vtable member usage | -43 | R_RISCV_ALIGN | Alignment statement | -44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | (CB-Type) -45 | R_RISCV_RVC_JUMP | PC-relative jump offset | (CJ-Type) -46 | R_RISCV_RVC_LUI | Absolute address | (CI-Type) -47 | R_RISCV_GPREL_I | GP-relative reference | (I-Type) -48 | R_RISCV_GPREL_S | GP-relative reference | (S-Type) -49 | R_RISCV_TPREL_I | TP-relative TLS LE load | (I-Type) -50 | R_RISCV_TPREL_S | TP-relative TLS LE store | (S-Type) -51 | R_RISCV_RELAX | Instruction pair can be relaxed | -52 | R_RISCV_SUB6 | Local label subtraction | -53 | R_RISCV_SET6 | Local label subtraction | -54 | R_RISCV_SET8 | Local label subtraction | -55 | R_RISCV_SET16 | Local label subtraction | -56 | R_RISCV_SET32 | Local label subtraction | -57 | R_RISCV_32_PCREL | PC-relative reference | word32 = S + A - PC -58 | R_RISCV_IRELATIVE | Runtime relocation | word32,64 = ifunc_resolver(B + A) -59-191 | *Reserved* | Reserved for future standard use | -192-255 | *Reserved* | Reserved for nonstandard ABI extensions | +Enum | ELF Reloc Type | Description | Field | Calculation | Details +:--- | :------------------ | :--------------- | :---- | :---------- | :------- +0 | R_RISCV_NONE | None | +1 | R_RISCV_32 | Runtime relocation | _word32_ | S + A +2 | R_RISCV_64 | Runtime relocation | _word64_ | S + A +3 | R_RISCV_RELATIVE | Runtime relocation | _wordclass_ | B + A +4 | R_RISCV_COPY | Runtime relocation | | | Must be in executable. not allowed in shared library +5 | R_RISCV_JUMP_SLOT | Runtime relocation | _wordclass_ | S | Handled by PLT unless `LD_BIND_NOW` +6 | R_RISCV_TLS_DTPMOD32 | TLS relocation | _word32_ | S->TLSINDEX +7 | R_RISCV_TLS_DTPMOD64 | TLS relocation | _word64_ | S->TLSINDEX +8 | R_RISCV_TLS_DTPREL32 | TLS relocation | _word32_ | S + A + TLS - TLS_TP_OFFSET +9 | R_RISCV_TLS_DTPREL64 | TLS relocation | _word64_ | S + A + TLS - TLS_TP_OFFSET +10 | R_RISCV_TLS_TPREL32 | TLS relocation | _word32_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET +11 | R_RISCV_TLS_TPREL64 | TLS relocation | _word64_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET +16 | R_RISCV_BRANCH | PC-relative branch | _B-Type_ | S + A - P +17 | R_RISCV_JAL | PC-relative jump | _UJ-Type_ | S + A - P +18 | R_RISCV_CALL | PC-relative call | _UJ-Type_ | S + A - P | Macros `call`, `tail` +19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _UJ-Type_ | S + A - P | Macros `call`, `tail` (PIC) +20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A | `%got_pcrel_hi(symbol)` +21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie` +22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd` +23 | R_RISCV_PCREL_HI20 | PC-relative reference | _U-Type_ | S + A - P | `%pcrel_hi(symbol)` +24 | R_RISCV_PCREL_LO12_I | PC-relative reference | _I-type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` +25 | R_RISCV_PCREL_LO12_S | PC-relative reference | _S-Type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` +26 | R_RISCV_HI20 | Absolute address | _U-Type_ | S + A | `%hi(symbol)` +27 | R_RISCV_LO12_I | Absolute address | _I-Type_ | S + A | `%lo(symbol)` +28 | R_RISCV_LO12_S | Absolute address | _S-Type_ | S + A | `%lo(symbol)` +29 | R_RISCV_TPREL_HI20 | TLS LE thread offset | _U-Type_ | | `%tprel_hi(symbol)` +30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | _I-Type_ | | `%tprel_lo(symbol)` +31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | _S-Type_ | | `%tprel_lo(symbol)` +32 | R_RISCV_TPREL_ADD | TLS LE thread usage | | | `%tprel_add(symbol)` +33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | S + A + V +34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | S + A + V +35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | S + A + V +36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | S + A + V +37 | R_RISCV_SUB8 | 8-bit label subtraction | _word8_ | V - S - A +38 | R_RISCV_SUB16 | 16-bit label subtraction | _word16_ | V - S - A +39 | R_RISCV_SUB32 | 32-bit label subtraction | _word32_ | V - S - A +40 | R_RISCV_SUB64 | 64-bit label subtraction | _word64_ | V - S - A +41 | R_RISCV_GNU_VTINHERIT | GNU C++ vtable hierarchy | +42 | R_RISCV_GNU_VTENTRY | GNU C++ vtable member usage | +43 | R_RISCV_ALIGN | Alignment statement | +44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | _CB-Type_ | S + A - P +45 | R_RISCV_RVC_JUMP | PC-relative jump offset | _CJ-Type_ | S + A - P +46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A - P +47 | R_RISCV_GPREL_I | GP-relative reference | _I-Type_ | S + A - GP +48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP +49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ +50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ +51 | R_RISCV_RELAX | Instruction pair can be relaxed | +52 | R_RISCV_SUB6 | Local label subtraction | +53 | R_RISCV_SET6 | Local label subtraction | +54 | R_RISCV_SET8 | Local label subtraction | +55 | R_RISCV_SET16 | Local label subtraction | +56 | R_RISCV_SET32 | Local label subtraction | +57 | R_RISCV_32_PCREL | PC-relative reference | _word32_ | S + A - P +58 | R_RISCV_IRELATIVE | Runtime relocation | _wordclass_ | `ifunc_resolver(B + A)` +59-191 | *Reserved* | Reserved for future standard use | +192-255 | *Reserved* | Reserved for nonstandard ABI extensions | Nonstandard extensions are free to use relocation numbers 192-255 for any purpose. These relocations may conflict with other nonstandard extensions. @@ -536,21 +536,43 @@ This section and later ones contain fragments written in assembler. The precise assembler syntax, including that of the relocations, is described in the [RISC-V Assembly Programmer's Manual](https://github.com/riscv/riscv-asm-manual). -### Address Calculation Symbols +### Calculation Symbols -The following table provides details on the variables used in address calculation: +The following table provides details on the variables used in relocation +calculation: -Variable | Description -:------------- | :---------------- -A | Addend field in the relocation entry associated with the symbol -B | Base address of a shared object loaded into memory -G | Offset of the symbol into the GOT (Global Offset Table) -S | Value of the symbol in the symbol table -GP | Value of `__global_pointer$` symbol. +Variable | Description +:------- | :---------------- +A | Addend field in the relocation entry associated with the symbol +B | Base address of a shared object loaded into memory +G | Offset of the symbol into the GOT (Global Offset Table) +P | Position of the relocation +S | Value of the symbol in the symbol table +V | Value at the position of the relocation +GP | Value of `__global_pointer$` symbol **Global Pointer**: It is assumed that program startup code will load the value of the `__global_pointer$` symbol into register `gp` (aka `x3`). +### Field Symbols + +The following table provides details on the variables used in relocation fields: + +Variable | Description +:------- | :---------- +_word8_ | Specifies an 8-bit field +_word16_ | Specifies a 16-bit field +_word32_ | Specifies a 32-bit field +_word64_ | Specifies a 64-bit field +_wordclass_ | Specifies a _word32_ field for ILP32 or a _word64_ field for LP64 +_CB-Type_ | Specifies a field as the immediate field in a CB-type instruction +_CI-Type_ | Specifies a field as the immediate field in a CI-type instruction +_CJ-Type_ | Specifies a field as the immediate field in a CJ-type instruction +_I-Type_ | Specifies a field as the immediate field in an I-type instruction +_S-Type_ | Specifies a field as the immediate field in an S-type instruction +_U-Type_ | Specifies a field as the immediate field in an U-type instruction +_UJ-Type_ | Specifies a field as the immediate field in an U-type and a J-type instruction + ### Absolute Addresses 32-bit absolute addresses in position dependent code are loaded with a pair @@ -951,4 +973,3 @@ there is no differentiation between ILP32 and LP64 abis. Here a combination of the **gABI** and the **psABI** * **gABI**: generic ABI * **psABI**: processor specific ABI - From 21aaa9d5063073f168d3e5b09b4a1afc2d782fc7 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Tue, 9 Jun 2020 16:30:52 -0500 Subject: [PATCH 02/18] Address comments by jim-wilson Use the instruction types per the current v2.2 ISA spec. --- riscv-elf.md | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 110a753b..c8e51d31 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -484,9 +484,9 @@ Enum | ELF Reloc Type | Description | Field | C 10 | R_RISCV_TLS_TPREL32 | TLS relocation | _word32_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET 11 | R_RISCV_TLS_TPREL64 | TLS relocation | _word64_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET 16 | R_RISCV_BRANCH | PC-relative branch | _B-Type_ | S + A - P -17 | R_RISCV_JAL | PC-relative jump | _UJ-Type_ | S + A - P -18 | R_RISCV_CALL | PC-relative call | _UJ-Type_ | S + A - P | Macros `call`, `tail` -19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _UJ-Type_ | S + A - P | Macros `call`, `tail` (PIC) +17 | R_RISCV_JAL | PC-relative jump | _J-Type_ | S + A - P +18 | R_RISCV_CALL | PC-relative call | _J-Type_ | S + A - P | Macros `call`, `tail` +19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _J-Type_ | S + A - P | Macros `call`, `tail` (PIC) 20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A | `%got_pcrel_hi(symbol)` 21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie` 22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd` @@ -565,13 +565,14 @@ _word16_ | Specifies a 16-bit field _word32_ | Specifies a 32-bit field _word64_ | Specifies a 64-bit field _wordclass_ | Specifies a _word32_ field for ILP32 or a _word64_ field for LP64 +_B-Type_ | Specifies a field as the immediate field in a B-type instruction _CB-Type_ | Specifies a field as the immediate field in a CB-type instruction _CI-Type_ | Specifies a field as the immediate field in a CI-type instruction _CJ-Type_ | Specifies a field as the immediate field in a CJ-type instruction _I-Type_ | Specifies a field as the immediate field in an I-type instruction _S-Type_ | Specifies a field as the immediate field in an S-type instruction _U-Type_ | Specifies a field as the immediate field in an U-type instruction -_UJ-Type_ | Specifies a field as the immediate field in an U-type and a J-type instruction +_J-Type_ | Specifies a field as the immediate field in a J-type instruction ### Absolute Addresses From f9bcf1a79bbf4145487ada819021620252e71cba Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Wed, 10 Jun 2020 18:11:09 -0500 Subject: [PATCH 03/18] Augument the information for DWARF relocations Add the missing information for the relocations intended primarily for DWARF records. --- riscv-elf.md | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index c8e51d31..b98cf9e3 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -475,7 +475,7 @@ Enum | ELF Reloc Type | Description | Field | C 1 | R_RISCV_32 | Runtime relocation | _word32_ | S + A 2 | R_RISCV_64 | Runtime relocation | _word64_ | S + A 3 | R_RISCV_RELATIVE | Runtime relocation | _wordclass_ | B + A -4 | R_RISCV_COPY | Runtime relocation | | | Must be in executable. not allowed in shared library +4 | R_RISCV_COPY | Runtime relocation | | | Must be in executable; not allowed in shared library 5 | R_RISCV_JUMP_SLOT | Runtime relocation | _wordclass_ | S | Handled by PLT unless `LD_BIND_NOW` 6 | R_RISCV_TLS_DTPMOD32 | TLS relocation | _word32_ | S->TLSINDEX 7 | R_RISCV_TLS_DTPMOD64 | TLS relocation | _word64_ | S->TLSINDEX @@ -500,10 +500,10 @@ Enum | ELF Reloc Type | Description | Field | C 30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | _I-Type_ | | `%tprel_lo(symbol)` 31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | _S-Type_ | | `%tprel_lo(symbol)` 32 | R_RISCV_TPREL_ADD | TLS LE thread usage | | | `%tprel_add(symbol)` -33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | S + A + V -34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | S + A + V -35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | S + A + V -36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | S + A + V +33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | V + S + A +34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | V + S + A +35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | V + S + A +36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | V + S + A 37 | R_RISCV_SUB8 | 8-bit label subtraction | _word8_ | V - S - A 38 | R_RISCV_SUB16 | 16-bit label subtraction | _word16_ | V - S - A 39 | R_RISCV_SUB32 | 32-bit label subtraction | _word32_ | V - S - A @@ -519,15 +519,15 @@ Enum | ELF Reloc Type | Description | Field | C 49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ 50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ 51 | R_RISCV_RELAX | Instruction pair can be relaxed | -52 | R_RISCV_SUB6 | Local label subtraction | -53 | R_RISCV_SET6 | Local label subtraction | -54 | R_RISCV_SET8 | Local label subtraction | -55 | R_RISCV_SET16 | Local label subtraction | -56 | R_RISCV_SET32 | Local label subtraction | +52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | V - S - A +53 | R_RISCV_SET6 | Local label assignment | _word6_ | S + A +54 | R_RISCV_SET8 | Local label assignment | _word8_ | S + A +55 | R_RISCV_SET16 | Local label assignment | _word16_ | S + A +56 | R_RISCV_SET32 | Local label assignment | _word32_ | S + A 57 | R_RISCV_32_PCREL | PC-relative reference | _word32_ | S + A - P 58 | R_RISCV_IRELATIVE | Runtime relocation | _wordclass_ | `ifunc_resolver(B + A)` -59-191 | *Reserved* | Reserved for future standard use | -192-255 | *Reserved* | Reserved for nonstandard ABI extensions | +59-191 | *Reserved* | Reserved for future standard use +192-255 | *Reserved* | Reserved for nonstandard ABI extensions Nonstandard extensions are free to use relocation numbers 192-255 for any purpose. These relocations may conflict with other nonstandard extensions. @@ -560,10 +560,11 @@ The following table provides details on the variables used in relocation fields: Variable | Description :------- | :---------- -_word8_ | Specifies an 8-bit field -_word16_ | Specifies a 16-bit field -_word32_ | Specifies a 32-bit field -_word64_ | Specifies a 64-bit field +_word6_ | Specifies the 6 least significant bits of a _word8_ field +_word8_ | Specifies an 8-bit word +_word16_ | Specifies a 16-bit word +_word32_ | Specifies a 32-bit word +_word64_ | Specifies a 64-bit word _wordclass_ | Specifies a _word32_ field for ILP32 or a _word64_ field for LP64 _B-Type_ | Specifies a field as the immediate field in a B-type instruction _CB-Type_ | Specifies a field as the immediate field in a CB-type instruction From 9d57333f1b02291fc17c1993e2b6974f575407ed Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Wed, 10 Jun 2020 18:35:42 -0500 Subject: [PATCH 04/18] Fix typo Fix the calculation of `R_RISCV_RVC_LUI`. --- riscv-elf.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-elf.md b/riscv-elf.md index b98cf9e3..cbc54802 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -513,7 +513,7 @@ Enum | ELF Reloc Type | Description | Field | C 43 | R_RISCV_ALIGN | Alignment statement | 44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | _CB-Type_ | S + A - P 45 | R_RISCV_RVC_JUMP | PC-relative jump offset | _CJ-Type_ | S + A - P -46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A - P +46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A 47 | R_RISCV_GPREL_I | GP-relative reference | _I-Type_ | S + A - GP 48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP 49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ From ffece567f5653d08a0b23b14a9b0074aeacb3367 Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Tue, 7 Jul 2020 16:13:46 +0100 Subject: [PATCH 05/18] Fix R_RISCV_GOT_HI20 calculation Despite its name it's PC-relative. --- riscv-elf.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-elf.md b/riscv-elf.md index cbc54802..714482f5 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -487,7 +487,7 @@ Enum | ELF Reloc Type | Description | Field | C 17 | R_RISCV_JAL | PC-relative jump | _J-Type_ | S + A - P 18 | R_RISCV_CALL | PC-relative call | _J-Type_ | S + A - P | Macros `call`, `tail` 19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _J-Type_ | S + A - P | Macros `call`, `tail` (PIC) -20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A | `%got_pcrel_hi(symbol)` +20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A - P | `%got_pcrel_hi(symbol)` 21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie` 22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd` 23 | R_RISCV_PCREL_HI20 | PC-relative reference | _U-Type_ | S + A - P | `%pcrel_hi(symbol)` From 3cfc3e59f216c84462ce6fbfa50463ab5d4fad2f Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 19 Jun 2020 17:07:32 -0500 Subject: [PATCH 06/18] riscv-elf.md: add description of the code models Add a brief descritption of the existing code models. --- riscv-elf.md | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/riscv-elf.md b/riscv-elf.md index 714482f5..c84b7294 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -10,6 +10,7 @@ * [ILP32E Calling Convention](#ilp32e-calling-convention) * [Named ABIs](#named-abis) * [Default ABIs](#default-abis) + * [Code models](#code-models) 3. [C type details](#c-types) * [C type sizes and alignments](#c-type-sizes) * [C type representations](#c-type-representation) @@ -320,6 +321,31 @@ default ABIs for specific architectures: * **on RV32G**: [ILP32D](#abi-ilp32d) +## Code models + +The RISC-V architecture constrains the addressing of positions in the +address space. There is no single instruction that can refer to an arbitrary +memory position using a literal as its argument. Rather, instructions exist +that, when combined together, can then be used to refer to a memory position +via its literal. And, when not, other data structures are used to help the +code to address the memory space. The coding conventions governing their use +are known as code models. + +### Medium low + +The medium low code model, or `medlow`, allows the code to address the lower +2 GiB of the address space. By using the instruction `lui` and `ld` or `addi` +instructions, for example, a 32-bit address literal can be produced. +This code model is not position independent. + +### Meidum any + +The medium any code model, or `medany`, allows the code to address the range +between -2 GiB and +2 GiB from its position. By using the instruction `auipc` +and `st` or `addi` instructions, for example, a signed 32-bit offset, relative +to the value of the `pc` register, can be produced. This code model is +position independent. + # C type details ## C type sizes and alignments From ac58ad3fce3554f86dd72c8e4e7f5b759b62e7a1 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 19 Jun 2020 18:06:51 -0500 Subject: [PATCH 07/18] riscv-elf.md: fix typo --- riscv-elf.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-elf.md b/riscv-elf.md index c84b7294..2ceafa49 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -338,7 +338,7 @@ The medium low code model, or `medlow`, allows the code to address the lower instructions, for example, a 32-bit address literal can be produced. This code model is not position independent. -### Meidum any +### Medium any The medium any code model, or `medany`, allows the code to address the range between -2 GiB and +2 GiB from its position. By using the instruction `auipc` From 5eeb7a7e7f62ce0fc2bc78d6578d10ceb14daaca Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 22 Jun 2020 17:08:48 -0500 Subject: [PATCH 08/18] riscv-elf.md: add description of the compact code model Additionally, address some comments by @jim-wilson and @lenari. --- riscv-elf.md | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 2ceafa49..2faefaa5 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -331,20 +331,34 @@ via its literal. And, when not, other data structures are used to help the code to address the memory space. The coding conventions governing their use are known as code models. -### Medium low +### Small -The medium low code model, or `medlow`, allows the code to address the lower -2 GiB of the address space. By using the instruction `lui` and `ld` or `addi` -instructions, for example, a 32-bit address literal can be produced. +The small code model, or `medlow`, allows the code to address the whole RV32 +address space or the lower 2 GiB of the RV64 address space. +By using the instructions `lui` and `ld` or `st`, when referring to an object, or +`addi`, when calculating an address literal, for example, +a 32-bit address literal can be produced. This code model is not position independent. -### Medium any - -The medium any code model, or `medany`, allows the code to address the range -between -2 GiB and +2 GiB from its position. By using the instruction `auipc` -and `st` or `addi` instructions, for example, a signed 32-bit offset, relative -to the value of the `pc` register, can be produced. This code model is -position independent. +### Medium + +The medium code model, or `medany`, allows the code to address the range +between -2 GiB and +2 GiB from its position. By using the instructions `auipc` +and `ld` or `st`, when referring to an object, or +`addi`, when calculating an address literal, for example, +a signed 32-bit offset, relative to the value of the `pc` register, +can be produced. +This code model is position independent. + +### Compact + +The compact code model allows the code to address the whole 64-bit address space, +especially when code and data are located far apart. By using the Global +Offset Table, or GOT, to hold the 64-bit address literals, any memory position +can be referred. By using the instructions `lui` and `addi`, a signed 32-bit +offset, relative to the value of the `gp` register, can be produced, referring +to address literals in the GOT. This code model is position independent. +Does not apply to the ILP32 ABIs. # C type details ## C type sizes and alignments From 9d5e0d3cb1ba4793c034273be478982272189993 Mon Sep 17 00:00:00 2001 From: Hsiangkai Wang Date: Fri, 21 Aug 2020 16:28:13 +0800 Subject: [PATCH 09/18] riscv-elf.md: define DWARF numbers for vector registers. --- riscv-elf.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/riscv-elf.md b/riscv-elf.md index 2faefaa5..e06853e1 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -971,7 +971,9 @@ Dwarf Number | Register Name | Description 0-31 | x0-x31 | Integer Registers 32-63 | f0-f31 | Floating-point Registers 64 | | Alternate Frame Return Column -65 - 3071 | | Reserved for future standard extensions +65-95 | | Reserved for future standard extensions +96-127 | v0-v31 | Vector Registers +128 - 3071 | | Reserved for future standard extensions 3072 - 4095 | | Reserved for custom extensions 4096 - 8191 | | CSRs From d9a02e8c62e3a3bd4a51cf5a14e92f658792cd40 Mon Sep 17 00:00:00 2001 From: Jim Wilson Date: Sat, 7 Nov 2020 11:56:47 -0800 Subject: [PATCH 10/18] Clean up R_RISCV_CALL* and R_RISCV_RELAX docs. R_RISCV_RELAX applies to previous reloc not to a pair of instructions. R_RISCV_CALL and R_RISCV_CALL_PLT are now interchangeable. --- riscv-elf.md | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index e06853e1..8c55754b 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -558,7 +558,7 @@ Enum | ELF Reloc Type | Description | Field | C 48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP 49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ 50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ -51 | R_RISCV_RELAX | Instruction pair can be relaxed | +51 | R_RISCV_RELAX | Previous reloc can be relaxed | 52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | V - S - A 53 | R_RISCV_SET6 | Local label assignment | _word6_ | S + A 54 | R_RISCV_SET8 | Local label assignment | _word8_ | S + A @@ -711,15 +711,19 @@ and fills in the GOT entry for subsequent calls to the function: ### Procedure Calls -`R_RISCV_CALL` or `R_RISCV_CALL_PLT` and `R_RISCV_RELAX` relocations are -associated with pairs of instructions (`AUIPC+JALR`) generated by the `CALL` -or `TAIL` pseudoinstructions. +`R_RISCV_CALL` and `R_RISCV_CALL_PLT` relocations are associated with +pairs of instructions (`AUIPC+JALR`) generated by the `CALL` or `TAIL` +pseudoinstructions. Originally, these relocations had slightly different +behavior, but that has turned out to be unnecessary, and they are now +interchangeable. -In position dependent code (`-fno-pic`) the `AUIPC` instruction in the +In position dependent code (`-fno-pic`), with relaxation enabled, +the `AUIPC` instruction in the `AUIPC+JALR` pair has both a `R_RISCV_CALL` relocation and a `R_RISCV_RELAX` relocation indicating the instruction sequence can be relaxed during linking. -In position independent code (`-fPIC`, `-fpic` or `-fpie`) the `AUIPC` +In position independent code (`-fPIC`, `-fpic` or `-fpie`), +with relaxation enabled, the `AUIPC` instruction in the `AUIPC+JALR` pair has both a `R_RISCV_CALL_PLT` relocation and a `R_RISCV_RELAX` relocation indicating the instruction sequence can be relaxed during linking. From c148f896e56f2d73c51a3260a867ee01576ca990 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 19 Jun 2020 17:52:07 -0500 Subject: [PATCH 11/18] riscv-elf.md: add new definitions for the compact code model Add the basic structures to support the compact code model. --- riscv-elf.md | 137 ++++++++++++++++++++++++++++----------------------- 1 file changed, 75 insertions(+), 62 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 8c55754b..e4081095 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -453,9 +453,9 @@ rules about 2✕XLEN aligned arguments being passed in "aligned" register pairs. * e_flags: Describes the format of this ELF file. These flags are used by the linker to disallow linking ELF files with incompatible ABIs together. - Bit 0 | Bit 1 - 2 | Bit 3 | Bit 4 | Bit 5 - 31 - -------|------------|-------|-------|------------ - RVC | Float ABI | RVE | TSO | *Reserved* + Bit 0 | Bit 1 - 2 | Bit 3 | Bit 4 | Bit 5 | Bit 6 - 31 + -------|------------|-------|-------|---------|------------ + RVC | Float ABI | RVE | TSO | Compact | *Reserved* * EF_RISCV_RVC (0x0001): This bit is set when the binary targets the C ABI, @@ -481,6 +481,8 @@ rules about 2✕XLEN aligned arguments being passed in "aligned" register pairs. * EF_RISCV_RVE (0x0008): This bit is set when the binary targets the E ABI. * EF_RISCV_TSO (0x0010): This bit is set when the binary requires the RVTSO memory consistency model. + * EF_RISCV_COMPACT (0x0020): This bit is set when the binary targets the + compact code model. Until such a time that the *Reserved* bits (0xffffffe0) are allocated by future versions of this specification, they shall not be set by standard @@ -509,65 +511,76 @@ Global Offset Table or DWARF meta data. The following table provides details of the RISC-V ELF relocations (instruction specific relocations show the instruction type in the Details column): -Enum | ELF Reloc Type | Description | Field | Calculation | Details -:--- | :------------------ | :--------------- | :---- | :---------- | :------- -0 | R_RISCV_NONE | None | -1 | R_RISCV_32 | Runtime relocation | _word32_ | S + A -2 | R_RISCV_64 | Runtime relocation | _word64_ | S + A -3 | R_RISCV_RELATIVE | Runtime relocation | _wordclass_ | B + A -4 | R_RISCV_COPY | Runtime relocation | | | Must be in executable; not allowed in shared library -5 | R_RISCV_JUMP_SLOT | Runtime relocation | _wordclass_ | S | Handled by PLT unless `LD_BIND_NOW` -6 | R_RISCV_TLS_DTPMOD32 | TLS relocation | _word32_ | S->TLSINDEX -7 | R_RISCV_TLS_DTPMOD64 | TLS relocation | _word64_ | S->TLSINDEX -8 | R_RISCV_TLS_DTPREL32 | TLS relocation | _word32_ | S + A + TLS - TLS_TP_OFFSET -9 | R_RISCV_TLS_DTPREL64 | TLS relocation | _word64_ | S + A + TLS - TLS_TP_OFFSET -10 | R_RISCV_TLS_TPREL32 | TLS relocation | _word32_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET -11 | R_RISCV_TLS_TPREL64 | TLS relocation | _word64_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET -16 | R_RISCV_BRANCH | PC-relative branch | _B-Type_ | S + A - P -17 | R_RISCV_JAL | PC-relative jump | _J-Type_ | S + A - P -18 | R_RISCV_CALL | PC-relative call | _J-Type_ | S + A - P | Macros `call`, `tail` -19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _J-Type_ | S + A - P | Macros `call`, `tail` (PIC) -20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A - P | `%got_pcrel_hi(symbol)` -21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie` -22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd` -23 | R_RISCV_PCREL_HI20 | PC-relative reference | _U-Type_ | S + A - P | `%pcrel_hi(symbol)` -24 | R_RISCV_PCREL_LO12_I | PC-relative reference | _I-type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` -25 | R_RISCV_PCREL_LO12_S | PC-relative reference | _S-Type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` -26 | R_RISCV_HI20 | Absolute address | _U-Type_ | S + A | `%hi(symbol)` -27 | R_RISCV_LO12_I | Absolute address | _I-Type_ | S + A | `%lo(symbol)` -28 | R_RISCV_LO12_S | Absolute address | _S-Type_ | S + A | `%lo(symbol)` -29 | R_RISCV_TPREL_HI20 | TLS LE thread offset | _U-Type_ | | `%tprel_hi(symbol)` -30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | _I-Type_ | | `%tprel_lo(symbol)` -31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | _S-Type_ | | `%tprel_lo(symbol)` -32 | R_RISCV_TPREL_ADD | TLS LE thread usage | | | `%tprel_add(symbol)` -33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | V + S + A -34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | V + S + A -35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | V + S + A -36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | V + S + A -37 | R_RISCV_SUB8 | 8-bit label subtraction | _word8_ | V - S - A -38 | R_RISCV_SUB16 | 16-bit label subtraction | _word16_ | V - S - A -39 | R_RISCV_SUB32 | 32-bit label subtraction | _word32_ | V - S - A -40 | R_RISCV_SUB64 | 64-bit label subtraction | _word64_ | V - S - A -41 | R_RISCV_GNU_VTINHERIT | GNU C++ vtable hierarchy | -42 | R_RISCV_GNU_VTENTRY | GNU C++ vtable member usage | -43 | R_RISCV_ALIGN | Alignment statement | -44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | _CB-Type_ | S + A - P -45 | R_RISCV_RVC_JUMP | PC-relative jump offset | _CJ-Type_ | S + A - P -46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A -47 | R_RISCV_GPREL_I | GP-relative reference | _I-Type_ | S + A - GP -48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP -49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ -50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ -51 | R_RISCV_RELAX | Previous reloc can be relaxed | -52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | V - S - A -53 | R_RISCV_SET6 | Local label assignment | _word6_ | S + A -54 | R_RISCV_SET8 | Local label assignment | _word8_ | S + A -55 | R_RISCV_SET16 | Local label assignment | _word16_ | S + A -56 | R_RISCV_SET32 | Local label assignment | _word32_ | S + A -57 | R_RISCV_32_PCREL | PC-relative reference | _word32_ | S + A - P -58 | R_RISCV_IRELATIVE | Runtime relocation | _wordclass_ | `ifunc_resolver(B + A)` -59-191 | *Reserved* | Reserved for future standard use -192-255 | *Reserved* | Reserved for nonstandard ABI extensions +Enum | ELF Reloc Type | Description | Field | Calculation | Details +:--- | :------------- | :---------- | :---- | :---------- | :------ +0 | R_RISCV_NONE | None | +1 | R_RISCV_32 | Runtime relocation | _word32_ | S + A +2 | R_RISCV_64 | Runtime relocation | _word64_ | S + A +3 | R_RISCV_RELATIVE | Runtime relocation | _wordclass_ | B + A +4 | R_RISCV_COPY | Runtime relocation | | | Must be in executable. not allowed in shared library +5 | R_RISCV_JUMP_SLOT | Runtime relocation | _wordclass_ | S | Handled by PLT unless `LD_BIND_NOW` +6 | R_RISCV_TLS_DTPMOD32 | TLS relocation | _word32_ | S->TLSINDEX +7 | R_RISCV_TLS_DTPMOD64 | TLS relocation | _word64_ | S->TLSINDEX +8 | R_RISCV_TLS_DTPREL32 | TLS relocation | _word32_ | S + A + TLS - TLS_TP_OFFSET +9 | R_RISCV_TLS_DTPREL64 | TLS relocation | _word64_ | S + A + TLS - TLS_TP_OFFSET +10 | R_RISCV_TLS_TPREL32 | TLS relocation | _word32_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET +11 | R_RISCV_TLS_TPREL64 | TLS relocation | _word64_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET +16 | R_RISCV_BRANCH | PC-relative branch | _B-Type_ | S + A - P +17 | R_RISCV_JAL | PC-relative jump | _J-Type_ | S + A - P +18 | R_RISCV_CALL | PC-relative call | _J-Type_ | S + A - P | Macros `call`, `tail` +19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _J-Type_ | S + A - P | Macros `call`, `tail` (PIC) +20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A | `%got_pcrel_hi(symbol)` +21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie` +22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd` +23 | R_RISCV_PCREL_HI20 | PC-relative reference | _U-Type_ | S + A - P | `%pcrel_hi(symbol)` +24 | R_RISCV_PCREL_LO12_I | PC-relative reference | _I-type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` +25 | R_RISCV_PCREL_LO12_S | PC-relative reference | _S-Type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` +26 | R_RISCV_HI20 | Absolute address | _U-Type_ | S + A | `%hi(symbol)` +27 | R_RISCV_LO12_I | Absolute address | _I-Type_ | S + A | `%lo(symbol)` +28 | R_RISCV_LO12_S | Absolute address | _S-Type_ | S + A | `%lo(symbol)` +29 | R_RISCV_TPREL_HI20 | TLS LE thread offset | _U-Type_ | | `%tprel_hi(symbol)` +30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | _I-Type_ | | `%tprel_lo(symbol)` +31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | _S-Type_ | | `%tprel_lo(symbol)` +32 | R_RISCV_TPREL_ADD | TLS LE thread usage | | | `%tprel_add(symbol)` +33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | S + A + V +34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | S + A + V +35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | S + A + V +36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | S + A + V +37 | R_RISCV_SUB8 | 8-bit label subtraction | _word8_ | V - S - A +38 | R_RISCV_SUB16 | 16-bit label subtraction | _word16_ | V - S - A +39 | R_RISCV_SUB32 | 32-bit label subtraction | _word32_ | V - S - A +40 | R_RISCV_SUB64 | 64-bit label subtraction | _word64_ | V - S - A +41 | R_RISCV_GNU_VTINHERIT | GNU C++ vtable hierarchy | +42 | R_RISCV_GNU_VTENTRY | GNU C++ vtable member usage | +43 | R_RISCV_ALIGN | Alignment statement | +44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | _CB-Type_ | S + A - P +45 | R_RISCV_RVC_JUMP | PC-relative jump offset | _CJ-Type_ | S + A - P +46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A - P +47 | R_RISCV_GPREL_I | GP-relative reference | _I-Type_ | S + A - GP +48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP +49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ +50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ +51 | R_RISCV_RELAX | Instruction pair can be relaxed | +52 | R_RISCV_SUB6 | Local label subtraction | +53 | R_RISCV_SET6 | Local label subtraction | +54 | R_RISCV_SET8 | Local label subtraction | +55 | R_RISCV_SET16 | Local label subtraction | +56 | R_RISCV_SET32 | Local label subtraction | +57 | R_RISCV_32_PCREL | PC-relative reference | _word32_ | S + A - P +58 | R_RISCV_IRELATIVE | Runtime relocation | _wordclass_ | `ifunc_resolver(B + A)` +59 | R_RISCV_64_PCREL | PC-relative reference | _word64_ | S + A - P +60 | R_RISCV_GPREL_HI20 | GP-relative reference | _U-type_ | S + A - GP | `%gprel_hi(symbol)` +61 | R_RISCV_GPREL_LO12_I | GP-relative reference | _I-type_ | S + A - GP | `%gprel_lo(symbol)` +62 | R_RISCV_GPREL_LO12_S | GP-relative reference | _S-type_ | S + A - GP | `%gprel_lo(symbol)` +63 | R_RISCV_GPREL_ADD | GP-relative usage | | | `%gprel(symbol)` +64 | R_RISCV_GPREL_LOAD | GP-relative usage | | | `%gprel(symbol)` +65 | R_RISCV_GOT_GPREL_HI20 | GP-relative GOT reference | _U-type_ | G + A - GP | `%got_gprel_hi(symbol)` +66 | R_RISCV_GOT_GPREL_LO12_I | GP-relative GOT reference | _I-type_ | G + A - GP | `%got_gprel_lo(symbol)` +67 | R_RISCV_GOT_GPREL_ADD | GP-relative GOT usage | | | `%got_gprel(symbol)` +68 | R_RISCV_GOT_GPREL_LOAD | GP-relative GOT usage | | | `%got_gprel(symbol)` +69 | R_RISCV_GOT_GPREL_STORE | GP-relative GOT usage | | | `%got_gprel(symbol)` +70-191 | *Reserved* | Reserved for future standard use | +192-255 | *Reserved* | Reserved for nonstandard ABI extensions | Nonstandard extensions are free to use relocation numbers 192-255 for any purpose. These relocations may conflict with other nonstandard extensions. From c6dc385550faa51ab914744d22078872a0420688 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Mon, 22 Jun 2020 17:18:44 -0500 Subject: [PATCH 12/18] riscv-elf.md: add missing relocation type Add the relocation type R_RISCV_GPREL_STORE. --- riscv-elf.md | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index e4081095..f07b723f 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -574,12 +574,13 @@ Enum | ELF Reloc Type | Description | Field 62 | R_RISCV_GPREL_LO12_S | GP-relative reference | _S-type_ | S + A - GP | `%gprel_lo(symbol)` 63 | R_RISCV_GPREL_ADD | GP-relative usage | | | `%gprel(symbol)` 64 | R_RISCV_GPREL_LOAD | GP-relative usage | | | `%gprel(symbol)` -65 | R_RISCV_GOT_GPREL_HI20 | GP-relative GOT reference | _U-type_ | G + A - GP | `%got_gprel_hi(symbol)` -66 | R_RISCV_GOT_GPREL_LO12_I | GP-relative GOT reference | _I-type_ | G + A - GP | `%got_gprel_lo(symbol)` -67 | R_RISCV_GOT_GPREL_ADD | GP-relative GOT usage | | | `%got_gprel(symbol)` -68 | R_RISCV_GOT_GPREL_LOAD | GP-relative GOT usage | | | `%got_gprel(symbol)` -69 | R_RISCV_GOT_GPREL_STORE | GP-relative GOT usage | | | `%got_gprel(symbol)` -70-191 | *Reserved* | Reserved for future standard use | +65 | R_RISCV_GPREL_STORE | GP-relative usage | | | `%gprel(symbol)` +66 | R_RISCV_GOT_GPREL_HI20 | GP-relative GOT reference | _U-type_ | G + A - GP | `%got_gprel_hi(symbol)` +67 | R_RISCV_GOT_GPREL_LO12_I | GP-relative GOT reference | _I-type_ | G + A - GP | `%got_gprel_lo(symbol)` +68 | R_RISCV_GOT_GPREL_ADD | GP-relative GOT usage | | | `%got_gprel(symbol)` +69 | R_RISCV_GOT_GPREL_LOAD | GP-relative GOT usage | | | `%got_gprel(symbol)` +70 | R_RISCV_GOT_GPREL_STORE | GP-relative GOT usage | | | `%got_gprel(symbol)` +71-191 | *Reserved* | Reserved for future standard use | 192-255 | *Reserved* | Reserved for nonstandard ABI extensions | Nonstandard extensions are free to use relocation numbers 192-255 for any From 6a66b485f86a00fb13c58ad3caacc4f9595b5dd9 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Thu, 25 Jun 2020 16:01:50 -0500 Subject: [PATCH 13/18] riscv-elf.md: remove EF_RISCV_COMPACT The compact code model can be linked with other code models, so the ELF header is probably not the best place for this information to reside. For LTO purposes, this information can be preserved in metadata. Additionally, remove some typos. --- riscv-elf.md | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index f07b723f..4a5fe28d 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -453,9 +453,9 @@ rules about 2✕XLEN aligned arguments being passed in "aligned" register pairs. * e_flags: Describes the format of this ELF file. These flags are used by the linker to disallow linking ELF files with incompatible ABIs together. - Bit 0 | Bit 1 - 2 | Bit 3 | Bit 4 | Bit 5 | Bit 6 - 31 - -------|------------|-------|-------|---------|------------ - RVC | Float ABI | RVE | TSO | Compact | *Reserved* + Bit 0 | Bit 1 - 2 | Bit 3 | Bit 4 | Bit 5 - 31 + -------|------------|-------|-------|------------ + RVC | Float ABI | RVE | TSO | _Reserved_ * EF_RISCV_RVC (0x0001): This bit is set when the binary targets the C ABI, @@ -481,8 +481,6 @@ rules about 2✕XLEN aligned arguments being passed in "aligned" register pairs. * EF_RISCV_RVE (0x0008): This bit is set when the binary targets the E ABI. * EF_RISCV_TSO (0x0010): This bit is set when the binary requires the RVTSO memory consistency model. - * EF_RISCV_COMPACT (0x0020): This bit is set when the binary targets the - compact code model. Until such a time that the *Reserved* bits (0xffffffe0) are allocated by future versions of this specification, they shall not be set by standard @@ -542,10 +540,10 @@ Enum | ELF Reloc Type | Description | Field 30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | _I-Type_ | | `%tprel_lo(symbol)` 31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | _S-Type_ | | `%tprel_lo(symbol)` 32 | R_RISCV_TPREL_ADD | TLS LE thread usage | | | `%tprel_add(symbol)` -33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | S + A + V -34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | S + A + V -35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | S + A + V -36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | S + A + V +33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | V + S + A +34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | V + S + A +35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | V + S + A +36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | V + S + A 37 | R_RISCV_SUB8 | 8-bit label subtraction | _word8_ | V - S - A 38 | R_RISCV_SUB16 | 16-bit label subtraction | _word16_ | V - S - A 39 | R_RISCV_SUB32 | 32-bit label subtraction | _word32_ | V - S - A @@ -555,17 +553,17 @@ Enum | ELF Reloc Type | Description | Field 43 | R_RISCV_ALIGN | Alignment statement | 44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | _CB-Type_ | S + A - P 45 | R_RISCV_RVC_JUMP | PC-relative jump offset | _CJ-Type_ | S + A - P -46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A - P +46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A 47 | R_RISCV_GPREL_I | GP-relative reference | _I-Type_ | S + A - GP 48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP 49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ 50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ -51 | R_RISCV_RELAX | Instruction pair can be relaxed | -52 | R_RISCV_SUB6 | Local label subtraction | -53 | R_RISCV_SET6 | Local label subtraction | -54 | R_RISCV_SET8 | Local label subtraction | -55 | R_RISCV_SET16 | Local label subtraction | -56 | R_RISCV_SET32 | Local label subtraction | +51 | R_RISCV_RELAX | Instruction pair can be relaxed | _word6_ | V - S - A +52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | S + A +53 | R_RISCV_SET6 | Local label assignment | _word6_ | S + A +54 | R_RISCV_SET8 | Local label assignment | _word8_ | S + A +55 | R_RISCV_SET16 | Local label assignment | _word16_ | S + A +56 | R_RISCV_SET32 | Local label assignment | _word32_ | S + A 57 | R_RISCV_32_PCREL | PC-relative reference | _word32_ | S + A - P 58 | R_RISCV_IRELATIVE | Runtime relocation | _wordclass_ | `ifunc_resolver(B + A)` 59 | R_RISCV_64_PCREL | PC-relative reference | _word64_ | S + A - P From dfa72d56f176d20da119d3156dc0e5973bcf02a5 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Thu, 25 Jun 2020 16:32:24 -0500 Subject: [PATCH 14/18] riscv-elf.md: fix typo --- riscv-elf.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 4a5fe28d..03af20b6 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -558,8 +558,8 @@ Enum | ELF Reloc Type | Description | Field 48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP 49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ 50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ -51 | R_RISCV_RELAX | Instruction pair can be relaxed | _word6_ | V - S - A -52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | S + A +51 | R_RISCV_RELAX | Instruction pair can be relaxed | +52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | V - S - A 53 | R_RISCV_SET6 | Local label assignment | _word6_ | S + A 54 | R_RISCV_SET8 | Local label assignment | _word8_ | S + A 55 | R_RISCV_SET16 | Local label assignment | _word16_ | S + A From d188bd194ad23eb456a6de8b31c1fcccfd17de1e Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 8 Jan 2021 11:38:22 -0600 Subject: [PATCH 15/18] riscv-elf.md: add TLS relocations Add the TLS relocations for the compact code model. --- riscv-elf.md | 148 +++++++++++++++++++++++++++------------------------ 1 file changed, 77 insertions(+), 71 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 03af20b6..07a12a8b 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -509,77 +509,83 @@ Global Offset Table or DWARF meta data. The following table provides details of the RISC-V ELF relocations (instruction specific relocations show the instruction type in the Details column): -Enum | ELF Reloc Type | Description | Field | Calculation | Details -:--- | :------------- | :---------- | :---- | :---------- | :------ -0 | R_RISCV_NONE | None | -1 | R_RISCV_32 | Runtime relocation | _word32_ | S + A -2 | R_RISCV_64 | Runtime relocation | _word64_ | S + A -3 | R_RISCV_RELATIVE | Runtime relocation | _wordclass_ | B + A -4 | R_RISCV_COPY | Runtime relocation | | | Must be in executable. not allowed in shared library -5 | R_RISCV_JUMP_SLOT | Runtime relocation | _wordclass_ | S | Handled by PLT unless `LD_BIND_NOW` -6 | R_RISCV_TLS_DTPMOD32 | TLS relocation | _word32_ | S->TLSINDEX -7 | R_RISCV_TLS_DTPMOD64 | TLS relocation | _word64_ | S->TLSINDEX -8 | R_RISCV_TLS_DTPREL32 | TLS relocation | _word32_ | S + A + TLS - TLS_TP_OFFSET -9 | R_RISCV_TLS_DTPREL64 | TLS relocation | _word64_ | S + A + TLS - TLS_TP_OFFSET -10 | R_RISCV_TLS_TPREL32 | TLS relocation | _word32_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET -11 | R_RISCV_TLS_TPREL64 | TLS relocation | _word64_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET -16 | R_RISCV_BRANCH | PC-relative branch | _B-Type_ | S + A - P -17 | R_RISCV_JAL | PC-relative jump | _J-Type_ | S + A - P -18 | R_RISCV_CALL | PC-relative call | _J-Type_ | S + A - P | Macros `call`, `tail` -19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _J-Type_ | S + A - P | Macros `call`, `tail` (PIC) -20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A | `%got_pcrel_hi(symbol)` -21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie` -22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd` -23 | R_RISCV_PCREL_HI20 | PC-relative reference | _U-Type_ | S + A - P | `%pcrel_hi(symbol)` -24 | R_RISCV_PCREL_LO12_I | PC-relative reference | _I-type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` -25 | R_RISCV_PCREL_LO12_S | PC-relative reference | _S-Type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` -26 | R_RISCV_HI20 | Absolute address | _U-Type_ | S + A | `%hi(symbol)` -27 | R_RISCV_LO12_I | Absolute address | _I-Type_ | S + A | `%lo(symbol)` -28 | R_RISCV_LO12_S | Absolute address | _S-Type_ | S + A | `%lo(symbol)` -29 | R_RISCV_TPREL_HI20 | TLS LE thread offset | _U-Type_ | | `%tprel_hi(symbol)` -30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | _I-Type_ | | `%tprel_lo(symbol)` -31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | _S-Type_ | | `%tprel_lo(symbol)` -32 | R_RISCV_TPREL_ADD | TLS LE thread usage | | | `%tprel_add(symbol)` -33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | V + S + A -34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | V + S + A -35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | V + S + A -36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | V + S + A -37 | R_RISCV_SUB8 | 8-bit label subtraction | _word8_ | V - S - A -38 | R_RISCV_SUB16 | 16-bit label subtraction | _word16_ | V - S - A -39 | R_RISCV_SUB32 | 32-bit label subtraction | _word32_ | V - S - A -40 | R_RISCV_SUB64 | 64-bit label subtraction | _word64_ | V - S - A -41 | R_RISCV_GNU_VTINHERIT | GNU C++ vtable hierarchy | -42 | R_RISCV_GNU_VTENTRY | GNU C++ vtable member usage | -43 | R_RISCV_ALIGN | Alignment statement | -44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | _CB-Type_ | S + A - P -45 | R_RISCV_RVC_JUMP | PC-relative jump offset | _CJ-Type_ | S + A - P -46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A -47 | R_RISCV_GPREL_I | GP-relative reference | _I-Type_ | S + A - GP -48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP -49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ -50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ -51 | R_RISCV_RELAX | Instruction pair can be relaxed | -52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | V - S - A -53 | R_RISCV_SET6 | Local label assignment | _word6_ | S + A -54 | R_RISCV_SET8 | Local label assignment | _word8_ | S + A -55 | R_RISCV_SET16 | Local label assignment | _word16_ | S + A -56 | R_RISCV_SET32 | Local label assignment | _word32_ | S + A -57 | R_RISCV_32_PCREL | PC-relative reference | _word32_ | S + A - P -58 | R_RISCV_IRELATIVE | Runtime relocation | _wordclass_ | `ifunc_resolver(B + A)` -59 | R_RISCV_64_PCREL | PC-relative reference | _word64_ | S + A - P -60 | R_RISCV_GPREL_HI20 | GP-relative reference | _U-type_ | S + A - GP | `%gprel_hi(symbol)` -61 | R_RISCV_GPREL_LO12_I | GP-relative reference | _I-type_ | S + A - GP | `%gprel_lo(symbol)` -62 | R_RISCV_GPREL_LO12_S | GP-relative reference | _S-type_ | S + A - GP | `%gprel_lo(symbol)` -63 | R_RISCV_GPREL_ADD | GP-relative usage | | | `%gprel(symbol)` -64 | R_RISCV_GPREL_LOAD | GP-relative usage | | | `%gprel(symbol)` -65 | R_RISCV_GPREL_STORE | GP-relative usage | | | `%gprel(symbol)` -66 | R_RISCV_GOT_GPREL_HI20 | GP-relative GOT reference | _U-type_ | G + A - GP | `%got_gprel_hi(symbol)` -67 | R_RISCV_GOT_GPREL_LO12_I | GP-relative GOT reference | _I-type_ | G + A - GP | `%got_gprel_lo(symbol)` -68 | R_RISCV_GOT_GPREL_ADD | GP-relative GOT usage | | | `%got_gprel(symbol)` -69 | R_RISCV_GOT_GPREL_LOAD | GP-relative GOT usage | | | `%got_gprel(symbol)` -70 | R_RISCV_GOT_GPREL_STORE | GP-relative GOT usage | | | `%got_gprel(symbol)` -71-191 | *Reserved* | Reserved for future standard use | -192-255 | *Reserved* | Reserved for nonstandard ABI extensions | +Enum | ELF Reloc Type | Description | Field | Calculation | Details +:--- | :------------- | :---------- | :---- | :---------- | :------ +0 | R_RISCV_NONE | None | +1 | R_RISCV_32 | Runtime relocation | _word32_ | S + A +2 | R_RISCV_64 | Runtime relocation | _word64_ | S + A +3 | R_RISCV_RELATIVE | Runtime relocation | _wordclass_ | B + A +4 | R_RISCV_COPY | Runtime relocation | | | Must be in executable. not allowed in shared library +5 | R_RISCV_JUMP_SLOT | Runtime relocation | _wordclass_ | S | Handled by PLT unless `LD_BIND_NOW` +6 | R_RISCV_TLS_DTPMOD32 | TLS relocation | _word32_ | S->TLSINDEX +7 | R_RISCV_TLS_DTPMOD64 | TLS relocation | _word64_ | S->TLSINDEX +8 | R_RISCV_TLS_DTPREL32 | TLS relocation | _word32_ | S + A + TLS - TLS_TP_OFFSET +9 | R_RISCV_TLS_DTPREL64 | TLS relocation | _word64_ | S + A + TLS - TLS_TP_OFFSET +10 | R_RISCV_TLS_TPREL32 | TLS relocation | _word32_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET +11 | R_RISCV_TLS_TPREL64 | TLS relocation | _word64_ | S + A + TLS + S_TLS_OFFSET - TLS_DTV_OFFSET +16 | R_RISCV_BRANCH | PC-relative branch | _B-Type_ | S + A - P +17 | R_RISCV_JAL | PC-relative jump | _J-Type_ | S + A - P +18 | R_RISCV_CALL | PC-relative call | _J-Type_ | S + A - P | Macros `call`, `tail` +19 | R_RISCV_CALL_PLT | PC-relative call (PLT) | _J-Type_ | S + A - P | Macros `call`, `tail` (PIC) +20 | R_RISCV_GOT_HI20 | PC-relative GOT reference | _U-Type_ | G + A | `%got_pcrel_hi(symbol)` +21 | R_RISCV_TLS_GOT_HI20 | PC-relative TLS IE GOT offset | _U-Type_ | | Macro `la.tls.ie` +22 | R_RISCV_TLS_GD_HI20 | PC-relative TLS GD reference | _U-Type_ | | Macro `la.tls.gd` +23 | R_RISCV_PCREL_HI20 | PC-relative reference | _U-Type_ | S + A - P | `%pcrel_hi(symbol)` +24 | R_RISCV_PCREL_LO12_I | PC-relative reference | _I-type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` +25 | R_RISCV_PCREL_LO12_S | PC-relative reference | _S-Type_ | S + A - P | `%pcrel_lo(address of %pcrel_hi)` +26 | R_RISCV_HI20 | Absolute address | _U-Type_ | S + A | `%hi(symbol)` +27 | R_RISCV_LO12_I | Absolute address | _I-Type_ | S + A | `%lo(symbol)` +28 | R_RISCV_LO12_S | Absolute address | _S-Type_ | S + A | `%lo(symbol)` +29 | R_RISCV_TPREL_HI20 | TLS LE thread offset | _U-Type_ | | `%tprel_hi(symbol)` +30 | R_RISCV_TPREL_LO12_I | TLS LE thread offset | _I-Type_ | | `%tprel_lo(symbol)` +31 | R_RISCV_TPREL_LO12_S | TLS LE thread offset | _S-Type_ | | `%tprel_lo(symbol)` +32 | R_RISCV_TPREL_ADD | TLS LE thread usage | | | `%tprel_add(symbol)` +33 | R_RISCV_ADD8 | 8-bit label addition | _word8_ | V + S + A +34 | R_RISCV_ADD16 | 16-bit label addition | _word16_ | V + S + A +35 | R_RISCV_ADD32 | 32-bit label addition | _word32_ | V + S + A +36 | R_RISCV_ADD64 | 64-bit label addition | _word64_ | V + S + A +37 | R_RISCV_SUB8 | 8-bit label subtraction | _word8_ | V - S - A +38 | R_RISCV_SUB16 | 16-bit label subtraction | _word16_ | V - S - A +39 | R_RISCV_SUB32 | 32-bit label subtraction | _word32_ | V - S - A +40 | R_RISCV_SUB64 | 64-bit label subtraction | _word64_ | V - S - A +41 | R_RISCV_GNU_VTINHERIT | GNU C++ vtable hierarchy | +42 | R_RISCV_GNU_VTENTRY | GNU C++ vtable member usage | +43 | R_RISCV_ALIGN | Alignment statement | +44 | R_RISCV_RVC_BRANCH | PC-relative branch offset | _CB-Type_ | S + A - P +45 | R_RISCV_RVC_JUMP | PC-relative jump offset | _CJ-Type_ | S + A - P +46 | R_RISCV_RVC_LUI | Absolute address | _CI-Type_ | S + A +47 | R_RISCV_GPREL_I | GP-relative reference | _I-Type_ | S + A - GP +48 | R_RISCV_GPREL_S | GP-relative reference | _S-Type_ | S + A - GP +49 | R_RISCV_TPREL_I | TP-relative TLS LE load | _I-Type_ +50 | R_RISCV_TPREL_S | TP-relative TLS LE store | _S-Type_ +51 | R_RISCV_RELAX | Instruction pair can be relaxed | +52 | R_RISCV_SUB6 | Local label subtraction | _word6_ | V - S - A +53 | R_RISCV_SET6 | Local label assignment | _word6_ | S + A +54 | R_RISCV_SET8 | Local label assignment | _word8_ | S + A +55 | R_RISCV_SET16 | Local label assignment | _word16_ | S + A +56 | R_RISCV_SET32 | Local label assignment | _word32_ | S + A +57 | R_RISCV_32_PCREL | PC-relative reference | _word32_ | S + A - P +58 | R_RISCV_IRELATIVE | Runtime relocation | _wordclass_ | `ifunc_resolver(B + A)` +59 | R_RISCV_64_PCREL | PC-relative reference | _word64_ | S + A - P +60 | R_RISCV_GPREL_HI20 | GP-relative reference | _U-type_ | S + A - GP | `%gprel_hi(symbol)` +61 | R_RISCV_GPREL_LO12_I | GP-relative reference | _I-type_ | S + A - GP | `%gprel_lo(symbol)` +62 | R_RISCV_GPREL_LO12_S | GP-relative reference | _S-type_ | S + A - GP | `%gprel_lo(symbol)` +63 | R_RISCV_GPREL_ADD | GP-relative usage | | | `%gprel_add(symbol)` +64 | R_RISCV_GPREL_LOAD | GP-relative usage | | | `%gprel(symbol)` +65 | R_RISCV_GPREL_STORE | GP-relative usage | | | `%gprel(symbol)` +66 | R_RISCV_GOT_GPREL_HI20 | GP-relative GOT reference | _U-type_ | G + A - GP | `%got_gprel_hi(symbol)` +67 | R_RISCV_GOT_GPREL_LO12_I | GP-relative GOT reference | _I-type_ | G + A - GP | `%got_gprel_lo(symbol)` +68 | R_RISCV_GOT_GPREL_ADD | GP-relative GOT usage | | | `%got_gprel_add(symbol)` +69 | R_RISCV_GOT_GPREL_LOAD | GP-relative GOT usage | | | `%got_gprel(symbol)` +70 | R_RISCV_GOT_GPREL_STORE | GP-relative GOT usage | | | `%got_gprel(symbol)` +71 | R_RISCV_TLS_GOT_GPREL_HI20 | GP-relative TLS GOT reference | | | Macro `la.tls.ie.gprel` +72 | R_RISCV_TLS_GOT_GPREL_LO20_I | GP-relative TLS GOT reference | | | Macro `la.tls.ie.gprel` +73 | R_RISCV_TLS_GOT_GPREL_ADD | GP-relative TLS GOT usage | | | `%tls_ie_gprel()` +74 | R_RISCV_TLS_GD_GPREL_HI20 | GP-relative TLS GD reference | | | Macro `la.tls.gd.gprel` +75 | R_RISCV_TLS_GD_GPREL_LO20_I | GP-relative TLS GD reference | | | Macro `la.tls.gd.gprel` +76 | R_RISCV_TLS_GD_GPREL_ADD | GP-relative TLS GD usage | | | `%tls_gd_gprel()` +77-191 | *Reserved* | Reserved for future standard use +192-255 | *Reserved* | Reserved for nonstandard ABI extensions Nonstandard extensions are free to use relocation numbers 192-255 for any purpose. These relocations may conflict with other nonstandard extensions. From 570e4e1444e21ea4fa44cea5527908538b8d04f4 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 8 Jan 2021 13:58:29 -0600 Subject: [PATCH 16/18] riscv-elf.md: update the PLT Add the PLT entries for the compact code model. --- riscv-elf.md | 51 +++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 43 insertions(+), 8 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 07a12a8b..61bb6ebd 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -700,8 +700,10 @@ GOT offsets lazily on the first call to any function, except when `LD_BIND_NOW` is set in which case the GOT entries are populated by the dynamic linker before the executable is started. Lazy resolution of GOT entries is intended to speed up program loading by deferring symbol -resolution to the first time the function is called. The first entry -in the PLT occupies two 16 byte entries: +resolution to the first time the function is called. + +For the small and medium code models, the first entry in the PLT occupies +two 16 byte entries: ``` 1: auipc t2, %pcrel_hi(.got.plt) @@ -714,18 +716,51 @@ in the PLT occupies two 16 byte entries: jr t3 ``` -Subsequent function entry stubs in the PLT take up 16 bytes and load a -function pointer from the GOT. On the first call to a function, the -entry redirects to the first PLT entry which calls `_dl_runtime_resolve` -and fills in the GOT entry for subsequent calls to the function: +For the compact code model, the third entry in the PLT has a stub that +calculates the absolute address of a function pointer in the GOT. +It occupies three 16 byte entries: + +``` +1: auipc t0, %hi_pcrel(2f) # address of 2f + addi t0, %lo_pcrel(1b) + ld t2, (t0) # difference between .got.plt - 2f + add t0, t0, t2 # address of .got.plt + add t0, t0, t3 # address of the function pointer + ld t3, (t0) # dereference the function pointer + jr t3 + nop + nop + nop +2: .quad .got.plt - ., 0 +``` + +For the small and medium code models, subsequent function entries in the PLT +take up 16 bytes and load a function pointer from the GOT. +On the first call to a function, the entry redirects to the first PLT entr +which calls `_dl_runtime_resolve` and fills in the GOT entry +for subsequent calls to the function: ``` -1: auipc t3, %pcrel_hi(function@.got.plt) - l[w|d] t3, %pcrel_lo(1b)(t3) +1: auipc t3, %pcrel_hi(function@.got.plt) # address of the function pointer + l[w|d] t3, %pcrel_lo(1b)(t3) # dereference the function pointer jalr t1, t3 nop ``` +For the compact code model, subsequent function entries in the PLT +take up 16 bytes and load a function pointer from the GOT. +On the first call to a function, the entry redirects to the first PLT entr +which calls `_dl_runtime_resolve` and fills in the GOT entry +for subsequent calls to the function: + +``` +1: lui t3, %hi(function@.got.plt - .got.plt) # offset to the function pointer + addi t3, %lo(function@.got.plt - .got.plt) + jal t1, stub@.plt + nop + +``` + ### Procedure Calls From 3a01132d806f11751423d72f8b1a4238c2438901 Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 29 Jan 2021 18:17:58 -0600 Subject: [PATCH 17/18] riscv-elf.md: fix typo --- riscv-elf.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index 61bb6ebd..b0234be6 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -455,7 +455,7 @@ rules about 2✕XLEN aligned arguments being passed in "aligned" register pairs. Bit 0 | Bit 1 - 2 | Bit 3 | Bit 4 | Bit 5 - 31 -------|------------|-------|-------|------------ - RVC | Float ABI | RVE | TSO | _Reserved_ + RVC | Float ABI | RVE | TSO | *Reserved* * EF_RISCV_RVC (0x0001): This bit is set when the binary targets the C ABI, @@ -716,7 +716,7 @@ two 16 byte entries: jr t3 ``` -For the compact code model, the third entry in the PLT has a stub that +For the compact code model, the first entry in the PLT has a stub that calculates the absolute address of a function pointer in the GOT. It occupies three 16 byte entries: @@ -726,7 +726,7 @@ It occupies three 16 byte entries: ld t2, (t0) # difference between .got.plt - 2f add t0, t0, t2 # address of .got.plt add t0, t0, t3 # address of the function pointer - ld t3, (t0) # dereference the function pointer + ld t3, (t0) # load the function pointer jr t3 nop nop From 789163fc717b26e3e918fee01164facabd3241ac Mon Sep 17 00:00:00 2001 From: Evandro Menezes Date: Fri, 29 Jan 2021 20:21:38 -0600 Subject: [PATCH 18/18] riscv-elf.md: add examples for TLS Add examples for the TLS pseudo instructions. --- riscv-elf.md | 58 +++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/riscv-elf.md b/riscv-elf.md index b0234be6..2f12db1b 100644 --- a/riscv-elf.md +++ b/riscv-elf.md @@ -571,20 +571,18 @@ Enum | ELF Reloc Type | Description | Fiel 61 | R_RISCV_GPREL_LO12_I | GP-relative reference | _I-type_ | S + A - GP | `%gprel_lo(symbol)` 62 | R_RISCV_GPREL_LO12_S | GP-relative reference | _S-type_ | S + A - GP | `%gprel_lo(symbol)` 63 | R_RISCV_GPREL_ADD | GP-relative usage | | | `%gprel_add(symbol)` -64 | R_RISCV_GPREL_LOAD | GP-relative usage | | | `%gprel(symbol)` -65 | R_RISCV_GPREL_STORE | GP-relative usage | | | `%gprel(symbol)` -66 | R_RISCV_GOT_GPREL_HI20 | GP-relative GOT reference | _U-type_ | G + A - GP | `%got_gprel_hi(symbol)` -67 | R_RISCV_GOT_GPREL_LO12_I | GP-relative GOT reference | _I-type_ | G + A - GP | `%got_gprel_lo(symbol)` -68 | R_RISCV_GOT_GPREL_ADD | GP-relative GOT usage | | | `%got_gprel_add(symbol)` -69 | R_RISCV_GOT_GPREL_LOAD | GP-relative GOT usage | | | `%got_gprel(symbol)` -70 | R_RISCV_GOT_GPREL_STORE | GP-relative GOT usage | | | `%got_gprel(symbol)` -71 | R_RISCV_TLS_GOT_GPREL_HI20 | GP-relative TLS GOT reference | | | Macro `la.tls.ie.gprel` -72 | R_RISCV_TLS_GOT_GPREL_LO20_I | GP-relative TLS GOT reference | | | Macro `la.tls.ie.gprel` -73 | R_RISCV_TLS_GOT_GPREL_ADD | GP-relative TLS GOT usage | | | `%tls_ie_gprel()` -74 | R_RISCV_TLS_GD_GPREL_HI20 | GP-relative TLS GD reference | | | Macro `la.tls.gd.gprel` -75 | R_RISCV_TLS_GD_GPREL_LO20_I | GP-relative TLS GD reference | | | Macro `la.tls.gd.gprel` -76 | R_RISCV_TLS_GD_GPREL_ADD | GP-relative TLS GD usage | | | `%tls_gd_gprel()` -77-191 | *Reserved* | Reserved for future standard use +64 | R_RISCV_GOT_GPREL_HI20 | GP-relative GOT reference | _U-type_ | G + A - GP | `%got_gprel_hi(symbol)` +65 | R_RISCV_GOT_GPREL_LO12_I | GP-relative GOT reference | _I-type_ | G + A - GP | `%got_gprel_lo(symbol)` +66 | R_RISCV_GOT_GPREL_ADD | GP-relative GOT usage | | | `%got_gprel_add(symbol)` +67 | R_RISCV_GOT_GPREL_LOAD | GP-relative GOT usage | | | `%got_gprel(symbol)` +68 | R_RISCV_GOT_GPREL_STORE | GP-relative GOT usage | | | `%got_gprel(symbol)` +69 | R_RISCV_TLS_GOT_GPREL_HI20 | GP-relative TLS GOT reference | | | Macro `la.tls.ie.gprel` +70 | R_RISCV_TLS_GOT_GPREL_LO20_I | GP-relative TLS GOT reference | | | Macro `la.tls.ie.gprel` +71 | R_RISCV_TLS_GOT_GPREL_ADD | GP-relative TLS GOT usage | | | `%tls_ie_gprel()` +72 | R_RISCV_TLS_GD_GPREL_HI20 | GP-relative TLS GD reference | | | Macro `la.tls.gd.gprel` +73 | R_RISCV_TLS_GD_GPREL_LO20_I | GP-relative TLS GD reference | | | Macro `la.tls.gd.gprel` +74 | R_RISCV_TLS_GD_GPREL_ADD | GP-relative TLS GD usage | | | `%tls_gd_gprel()` +75-191 | *Reserved* | Reserved for future standard use 192-255 | *Reserved* | Reserved for nonstandard ABI extensions Nonstandard extensions are free to use relocation numbers 192-255 for any @@ -956,6 +954,22 @@ label: {ld,lw} a5, 0(a5) # R_RISCV_PCREL_LO12_I (label) ``` +For the compact code model, +the pseudoinstruction `la.tls.ie.gprel` is used instead: + +``` + la.tls.ie.gprel a5, symbol, gp +``` + +Assuming that the `gp` register holds the value of `__global_pointer$`, +it expands to the following assembly instructions and relocations: + +``` + lui a5, %tls_ie_gprel_hi(symbol) # R_RISCV_TLS_GOT_GPREL_HI20 (symbol) + add a5, gp, a5, %tls_ie_gprel(symbol) # R_RISCV_TLS_GOT_GPREL_ADD (symbol) + addi a5, a5, %tls_ie_gprel_lo(symbol) # R_RISCV_TLS_GOT_GPREL_LO12_I (symbol) +``` + ### Global Dynamic @@ -995,6 +1009,22 @@ label: addi a0,a0,0 # R_RISCV_PCREL_LO12_I (label) ``` +For the compact code model, +the pseudoinstruction `la.tls.gd.gprel` is used instead: + +``` + la.tls.gd.gprel a5, symbol, t0 +``` + +Assuming that the `t0` register holds the value of `__global_pointer$`, +it expands to the following assembly instructions and relocations: + +``` + lui a5, %tls_gd_gprel_hi(symbol) # R_RISCV_TLS_GD_GPREL_HI20 (symbol) + add a5, gp, a5, %tls_gd_gprel(symbol) # R_RISCV_TLS_GD_GPREL_ADD (symbol) + addi a5, a5, %tls_gd_gprel_lo(symbol) # R_RISCV_TLS_GD_GPREL_LO12_I (symbol) +``` + In the Global Dynamic model, the runtime library provides the `__tls_get_addr` function: ```