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Removed version info from the table of vendor extensions.
The version number is not relevant for this table. However, to include an extension to this table, the ISA documentation must reference a stable or frozen version of the extension that is ready for implementation in the open-source toolchains like LLVM and GCC.
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‎src/toolchain-conventions.adoc‎

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@@ -348,38 +348,38 @@ tag to provide extra relocations for a given vendor.
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=== List of vendor extensions
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.List of vendor extensions
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[cols="20,20,10,~"]
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[cols="20,20,~"]
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|===
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|*Vendor* |*Name* |*Version* |*ISA Document*
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|OpenHW | Xcvalu | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvbi | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvbitmanip | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvelw | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvhwlp | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvmac | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvmem | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvsimd | 1.0.0 | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|SiFive | XSFvqmaccdod | 1.0 | https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification[SiFive Int8 Matrix Multiplication Extensions Specification]
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|SiFive | XSFvqmaccqoq | 1.0 | https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification[SiFive Int8 Matrix Multiplication Extensions Specification]
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|SiFive | XSFvfnrclipxfqf | 1.0 | https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions[FP32-to-int8 Ranged Clip Instructions (Xsfvfnrclipxfqf) Extension Specification]
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|SiFive | Xsfvfwmaccqqq | 1.0 | https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction[Matrix Multiply Accumulate Instruction (Xsfvfwmaccqqq) Extension Specification]
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|SiFive | XSFVCP | 1.0 | https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf[SiFive Vector Coprocessor Interface Software Specification]
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|T-Head | XTheadCmo | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadBa | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadBb | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadBs | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadCondMov | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadFMemIdx | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadFmv | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadInt | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadMac | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadMemPair | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadMemIdx | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadSync | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadVector | 1.0 | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|Ventana | XVentanaCondOps | 1.0 | https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf[VTx-family custom instructions]
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|MIPS | Xmipscmov | 1.0 | https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf[MIPS P8700 Programmer's Guide]
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|MIPS | Xmipslsp | 1.0 | https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf[MIPS P8700 Programmer's Guide]
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|*Vendor* |*Name* |*ISA Document*
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|OpenHW | Xcvalu | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvbi | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvbitmanip | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvelw | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvhwlp | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvmac | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvmem | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|OpenHW | Xcvsimd | https://github.com/openhwgroup/cv32e40p/blob/dev/docs/source/instruction_set_extensions.rst[CORE-V Instruction Set Extensions]
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|SiFive | XSFvqmaccdod | https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification[SiFive Int8 Matrix Multiplication Extensions Specification]
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|SiFive | XSFvqmaccqoq | https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification[SiFive Int8 Matrix Multiplication Extensions Specification]
364+
|SiFive | XSFvfnrclipxfqf | https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions[FP32-to-int8 Ranged Clip Instructions (Xsfvfnrclipxfqf) Extension Specification]
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|SiFive | Xsfvfwmaccqqq | https://www.sifive.com/document-file/matrix-multiply-accumulate-instruction[Matrix Multiply Accumulate Instruction (Xsfvfwmaccqqq) Extension Specification]
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|SiFive | XSFVCP | https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf[SiFive Vector Coprocessor Interface Software Specification]
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|T-Head | XTheadCmo | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadBa | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadBb | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadBs | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadCondMov | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadFMemIdx | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadFmv | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadInt | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadMac | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadMemPair | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadMemIdx | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadSync | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|T-Head | XTheadVector | https://github.com/T-head-Semi/thead-extension-spec/releases/latest[T-Head ISA extension specification]
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|Ventana | XVentanaCondOps | https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf[VTx-family custom instructions]
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|MIPS | Xmipscmov | https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf[MIPS P8700 Programmer's Guide]
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|MIPS | Xmipslsp | https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf[MIPS P8700 Programmer's Guide]
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|===
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NOTE: Vendor extension names are case-insensitive, CamelCase is used here

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