Merge pull request #28 from riscv-rust/svd2rust_up

update for svd2rust v0.26.0

Author: almindor

CHANGELOG.md

@@ -17,7 +17,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - Update `riscv` dependency to version 0.8
-- Update Minimum Supported Rust Version to 1.59
 - Regenerate code with `svd2rust` v0.19.0
 
 ### Fixed

Cargo.toml

@@ -10,8 +10,8 @@ license = "ISC"
 rust-version = "1.59"
 
 [dependencies]
+critical-section = { version = "1.1.1", optional = true }
 vcell = "0.1.3"
-riscv = "0.10.1"
 
 [features]
 rt = []

src/common/aonclk.rs renamed to src/aonclk.rs

@@ -3,9 +3,9 @@
 pub struct RegisterBlock {
     _reserved0: [u8; 0x70],
     #[doc = "0x70 - AON Clock Configuration Register"]
-    pub lfrosccfg: crate::Reg<lfrosccfg::LFROSCCFG_SPEC>,
+    pub lfrosccfg: LFROSCCFG,
 }
-#[doc = "lfrosccfg register accessor: an alias for `Reg<LFROSCCFG_SPEC>`"]
+#[doc = "lfrosccfg (rw) register accessor: an alias for `Reg<LFROSCCFG_SPEC>`"]
 pub type LFROSCCFG = crate::Reg<lfrosccfg::LFROSCCFG_SPEC>;
 #[doc = "AON Clock Configuration Register"]
 pub mod lfrosccfg;

src/aonclk/lfrosccfg.rs

@@ -0,0 +1,122 @@
+#[doc = "Register `lfrosccfg` reader"]
+pub struct R(crate::R<LFROSCCFG_SPEC>);
+impl core::ops::Deref for R {
+    type Target = crate::R<LFROSCCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl From<crate::R<LFROSCCFG_SPEC>> for R {
+    #[inline(always)]
+    fn from(reader: crate::R<LFROSCCFG_SPEC>) -> Self {
+        R(reader)
+    }
+}
+#[doc = "Register `lfrosccfg` writer"]
+pub struct W(crate::W<LFROSCCFG_SPEC>);
+impl core::ops::Deref for W {
+    type Target = crate::W<LFROSCCFG_SPEC>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+impl core::ops::DerefMut for W {
+    #[inline(always)]
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
+impl From<crate::W<LFROSCCFG_SPEC>> for W {
+    #[inline(always)]
+    fn from(writer: crate::W<LFROSCCFG_SPEC>) -> Self {
+        W(writer)
+    }
+}
+#[doc = "Field `div` reader - "]
+pub type DIV_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `div` writer - "]
+pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LFROSCCFG_SPEC, u8, u8, 6, O>;
+#[doc = "Field `trim` reader - "]
+pub type TRIM_R = crate::FieldReader<u8, u8>;
+#[doc = "Field `trim` writer - "]
+pub type TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LFROSCCFG_SPEC, u8, u8, 5, O>;
+#[doc = "Field `enable` reader - "]
+pub type ENABLE_R = crate::BitReader<bool>;
+#[doc = "Field `enable` writer - "]
+pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LFROSCCFG_SPEC, bool, O>;
+#[doc = "Field `ready` reader - "]
+pub type READY_R = crate::BitReader<bool>;
+#[doc = "Field `ready` writer - "]
+pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u32, LFROSCCFG_SPEC, bool, O>;
+impl R {
+    #[doc = "Bits 0:5"]
+    #[inline(always)]
+    pub fn div(&self) -> DIV_R {
+        DIV_R::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bits 16:20"]
+    #[inline(always)]
+    pub fn trim(&self) -> TRIM_R {
+        TRIM_R::new(((self.bits >> 16) & 0x1f) as u8)
+    }
+    #[doc = "Bit 30"]
+    #[inline(always)]
+    pub fn enable(&self) -> ENABLE_R {
+        ENABLE_R::new(((self.bits >> 30) & 1) != 0)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn ready(&self) -> READY_R {
+        READY_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bits 0:5"]
+    #[inline(always)]
+    pub fn div(&mut self) -> DIV_W<0> {
+        DIV_W::new(self)
+    }
+    #[doc = "Bits 16:20"]
+    #[inline(always)]
+    pub fn trim(&mut self) -> TRIM_W<16> {
+        TRIM_W::new(self)
+    }
+    #[doc = "Bit 30"]
+    #[inline(always)]
+    pub fn enable(&mut self) -> ENABLE_W<30> {
+        ENABLE_W::new(self)
+    }
+    #[doc = "Bit 31"]
+    #[inline(always)]
+    pub fn ready(&mut self) -> READY_W<31> {
+        READY_W::new(self)
+    }
+    #[doc = "Writes raw bits to the register."]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.0.bits(bits);
+        self
+    }
+}
+#[doc = "AON Clock Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lfrosccfg](index.html) module"]
+pub struct LFROSCCFG_SPEC;
+impl crate::RegisterSpec for LFROSCCFG_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [lfrosccfg::R](R) reader structure"]
+impl crate::Readable for LFROSCCFG_SPEC {
+    type Reader = R;
+}
+#[doc = "`write(|w| ..)` method takes [lfrosccfg::W](W) writer structure"]
+impl crate::Writable for LFROSCCFG_SPEC {
+    type Writer = W;
+}
+#[doc = "`reset()` method sets lfrosccfg to value 0"]
+impl crate::Resettable for LFROSCCFG_SPEC {
+    #[inline(always)]
+    fn reset_value() -> Self::Ux {
+        0
+    }
+}

src/common/backup.rs renamed to src/backup.rs

@@ -3,9 +3,9 @@
 pub struct RegisterBlock {
     _reserved0: [u8; 0x80],
     #[doc = "0x80..0xc0 - Backup Register"]
-    pub backup: [crate::Reg<backup::BACKUP_SPEC>; 16],
+    pub backup: [BACKUP; 16],
 }
-#[doc = "backup register accessor: an alias for `Reg<BACKUP_SPEC>`"]
+#[doc = "backup (rw) register accessor: an alias for `Reg<BACKUP_SPEC>`"]
 pub type BACKUP = crate::Reg<backup::BACKUP_SPEC>;
 #[doc = "Backup Register"]
 pub mod backup;

src/common/backup/backup.rs renamed to src/backup/backup.rs

@@ -2,35 +2,35 @@
 #[repr(C)]
 pub struct RegisterBlock {
     #[doc = "0x00 - Hart 0 software interrupt register"]
-    pub msip: crate::Reg<msip::MSIP_SPEC>,
+    pub msip: MSIP,
     _reserved1: [u8; 0x3ffc],
     #[doc = "0x4000 - Hart 0 time comparator register"]
-    pub mtimecmp: crate::Reg<mtimecmp::MTIMECMP_SPEC>,
+    pub mtimecmp: MTIMECMP,
     #[doc = "0x4004 - Hart 0 time comparator register"]
-    pub mtimecmph: crate::Reg<mtimecmph::MTIMECMPH_SPEC>,
+    pub mtimecmph: MTIMECMPH,
     _reserved3: [u8; 0x7ff0],
     #[doc = "0xbff8 - Timer register"]
-    pub mtime: crate::Reg<mtime::MTIME_SPEC>,
+    pub mtime: MTIME,
     #[doc = "0xbffc - Timer register"]
-    pub mtimeh: crate::Reg<mtimeh::MTIMEH_SPEC>,
+    pub mtimeh: MTIMEH,
 }
-#[doc = "msip register accessor: an alias for `Reg<MSIP_SPEC>`"]
+#[doc = "msip (rw) register accessor: an alias for `Reg<MSIP_SPEC>`"]
 pub type MSIP = crate::Reg<msip::MSIP_SPEC>;
 #[doc = "Hart 0 software interrupt register"]
 pub mod msip;
-#[doc = "mtimecmp register accessor: an alias for `Reg<MTIMECMP_SPEC>`"]
+#[doc = "mtimecmp (rw) register accessor: an alias for `Reg<MTIMECMP_SPEC>`"]
 pub type MTIMECMP = crate::Reg<mtimecmp::MTIMECMP_SPEC>;
 #[doc = "Hart 0 time comparator register"]
 pub mod mtimecmp;
-#[doc = "mtimecmph register accessor: an alias for `Reg<MTIMECMPH_SPEC>`"]
+#[doc = "mtimecmph (rw) register accessor: an alias for `Reg<MTIMECMPH_SPEC>`"]
 pub type MTIMECMPH = crate::Reg<mtimecmph::MTIMECMPH_SPEC>;
 #[doc = "Hart 0 time comparator register"]
 pub mod mtimecmph;
-#[doc = "mtime register accessor: an alias for `Reg<MTIME_SPEC>`"]
+#[doc = "mtime (rw) register accessor: an alias for `Reg<MTIME_SPEC>`"]
 pub type MTIME = crate::Reg<mtime::MTIME_SPEC>;
 #[doc = "Timer register"]
 pub mod mtime;
-#[doc = "mtimeh register accessor: an alias for `Reg<MTIMEH_SPEC>`"]
+#[doc = "mtimeh (rw) register accessor: an alias for `Reg<MTIMEH_SPEC>`"]
 pub type MTIMEH = crate::Reg<mtimeh::MTIMEH_SPEC>;
 #[doc = "Timer register"]
 pub mod mtimeh;