From c31967e1b83f7b413ff295ee139edb07082fdbdf Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 07:45:10 +0200 Subject: [PATCH 1/2] Update PAC --- Cargo.toml | 3 +- src/eclic.rs | 107 ++++++++++++++++++++------------------------------- 2 files changed, 43 insertions(+), 67 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 158fc8f..0b5dc88 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -10,7 +10,8 @@ license = "ISC" edition = "2018" [dependencies] -gd32vf103-pac = "0.4.0" +# critical-section only required for doctests +gd32vf103-pac = { version = "0.5.0", features = ["critical-section"] } riscv = "0.6.0" nb = "0.1.2" void = { version = "1.0.2", default-features = false } diff --git a/src/eclic.rs b/src/eclic.rs index 071892c..20b3060 100644 --- a/src/eclic.rs +++ b/src/eclic.rs @@ -1,5 +1,4 @@ -use crate::pac::ECLIC; -use riscv::interrupt::Nr; +use crate::pac::{ECLIC, Interrupt}; const EFFECTIVE_LEVEL_PRIORITY_BITS: u8 = 4; @@ -84,43 +83,43 @@ pub trait EclicExt { fn get_priority_bits() -> u8; /// Setup `interrupt` - fn setup(interrupt: I, tt: TriggerType, level: Level, priority: Priority); + fn setup(interrupt: Interrupt, tt: TriggerType, level: Level, priority: Priority); /// Enables `interrupt` - unsafe fn unmask(interrupt: I); + unsafe fn unmask(interrupt: Interrupt); /// Disables `interrupt` - fn mask(interrupt: I); + fn mask(interrupt: Interrupt); /// Checks if `interrupt` is enabled - fn is_enabled(interrupt: I) -> bool; + fn is_enabled(interrupt: Interrupt) -> bool; /// Forces `interrupt` into pending state - fn pend(interrupt: I); + fn pend(interrupt: Interrupt); /// Clears `interrupt`'s pending state - fn unpend(interrupt: I); + fn unpend(interrupt: Interrupt); /// Checks if `interrupt` is pending - fn is_pending(interrupt: I) -> bool; + fn is_pending(interrupt: Interrupt) -> bool; /// Set `interrupt` trigger type - fn set_trigger_type(interrupt: I, tt: TriggerType); + fn set_trigger_type(interrupt: Interrupt, tt: TriggerType); /// Get `interrupt` trigger type - fn get_trigger_type(interrupt: I) -> Option; + fn get_trigger_type(interrupt: Interrupt) -> Option; // Set `interrupt` level - fn set_level(interrupt: I, level: Level); + fn set_level(interrupt: Interrupt, level: Level); // Get `interrupt` level - fn get_level(interrupt: I) -> Level; + fn get_level(interrupt: Interrupt) -> Level; // Set `interrupt` priority - fn set_priority(interrupt: I, priority: Priority); + fn set_priority(interrupt: Interrupt, priority: Priority); // Get `interrupt` interrupt - fn get_priority(interrupt: I) -> Priority; + fn get_priority(interrupt: Interrupt) -> Priority; } impl EclicExt for ECLIC { @@ -181,7 +180,7 @@ impl EclicExt for ECLIC { EFFECTIVE_LEVEL_PRIORITY_BITS - Self::get_level_bits() } - fn setup(interrupt: I, tt: TriggerType, level: Level, priority: Priority) { + fn setup(interrupt: Interrupt, tt: TriggerType, level: Level, priority: Priority) { Self::mask(interrupt); Self::set_trigger_type(interrupt, tt); Self::set_level(interrupt, level); @@ -190,31 +189,25 @@ impl EclicExt for ECLIC { } #[inline] - unsafe fn unmask(interrupt: I) { - let nr = usize::from(interrupt.nr()); - - (*Self::ptr()).clicints[nr] + unsafe fn unmask(interrupt: Interrupt) { + (*Self::ptr()).clicints[interrupt as usize] .clicintie .write(|w| w.ie().set_bit()) } #[inline] - fn mask(interrupt: I) { - let nr = usize::from(interrupt.nr()); - + fn mask(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintie .write(|w| w.ie().clear_bit()) } } #[inline] - fn is_enabled(interrupt: I) -> bool { - let nr = usize::from(interrupt.nr()); - + fn is_enabled(interrupt: Interrupt) -> bool { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintie .read() .ie() @@ -223,33 +216,27 @@ impl EclicExt for ECLIC { } #[inline] - fn pend(interrupt: I) { - let nr = usize::from(interrupt.nr()); - + fn pend(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintip .write(|w| w.ip().set_bit()) } } #[inline] - fn unpend(interrupt: I) { - let nr = usize::from(interrupt.nr()); - + fn unpend(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintip .write(|w| w.ip().clear_bit()) } } #[inline] - fn is_pending(interrupt: I) -> bool { - let nr = usize::from(interrupt.nr()); - + fn is_pending(interrupt: Interrupt) -> bool { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintip .read() .ip() @@ -258,21 +245,17 @@ impl EclicExt for ECLIC { } #[inline] - fn set_trigger_type(interrupt: I, tt: TriggerType) { - let nr = usize::from(interrupt.nr()); - + fn set_trigger_type(interrupt: Interrupt, tt: TriggerType) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintattr .write(|w| w.trig().bits(tt as u8).shv().clear_bit()) } } #[inline] - fn get_trigger_type(interrupt: I) -> Option { - let nr = usize::from(interrupt.nr()); - - match unsafe { (*Self::ptr()).clicints[nr].clicintattr.read().trig().bits() } { + fn get_trigger_type(interrupt: Interrupt) -> Option { + match unsafe { (*Self::ptr()).clicints[interrupt as usize].clicintattr.read().trig().bits() } { 0 => Some(TriggerType::Level), 1 => Some(TriggerType::RisingEdge), 3 => Some(TriggerType::FallingEdge), @@ -281,11 +264,9 @@ impl EclicExt for ECLIC { } #[inline] - fn set_level(interrupt: I, level: Level) { - let nr = usize::from(interrupt.nr()); - + fn set_level(interrupt: Interrupt, level: Level) { let mut intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() @@ -300,18 +281,16 @@ impl EclicExt for ECLIC { let level = level << (8 - level_bits); unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .write(|w| w.level_priority().bits(intctl | level)) } } #[inline] - fn get_level(interrupt: I) -> Level { - let nr = usize::from(interrupt.nr()); - + fn get_level(interrupt: Interrupt) -> Level { let intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() @@ -325,11 +304,9 @@ impl EclicExt for ECLIC { } #[inline] - fn set_priority(interrupt: I, priority: Priority) { - let nr = usize::from(interrupt.nr()); - + fn set_priority(interrupt: Interrupt, priority: Priority) { let mut intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() @@ -347,18 +324,16 @@ impl EclicExt for ECLIC { let priority = priority << (8 - EFFECTIVE_LEVEL_PRIORITY_BITS); unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .write(|w| w.level_priority().bits(intctl | priority)) } } #[inline] - fn get_priority(interrupt: I) -> Priority { - let nr = usize::from(interrupt.nr()); - + fn get_priority(interrupt: Interrupt) -> Priority { let intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() From 6ceedd0c81c5d473ec7ea7f0648e9a2282fd6f83 Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 08:34:22 +0200 Subject: [PATCH 2/2] Update riscv Without the Nr trait in PAC, risc-v can be independently updated --- Cargo.toml | 2 +- src/gpio.rs | 2 +- src/rcu.rs | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 0b5dc88..34317b1 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -12,7 +12,7 @@ edition = "2018" [dependencies] # critical-section only required for doctests gd32vf103-pac = { version = "0.5.0", features = ["critical-section"] } -riscv = "0.6.0" +riscv = "0.15.0" nb = "0.1.2" void = { version = "1.0.2", default-features = false } cast = { version = "0.2.3", default-features = false } diff --git a/src/gpio.rs b/src/gpio.rs index 8cced3c..7984d72 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -117,7 +117,7 @@ trait PeripheralAccess { let value = (bits as u32) << offset; let regs = Self::peripheral(); - interrupt::free(|_| { + interrupt::free(|| { if index < 8 { regs.ctl0.modify(|r, w| unsafe { w.bits((r.bits() & mask) | value) diff --git a/src/rcu.rs b/src/rcu.rs index 5aa694e..2203285 100644 --- a/src/rcu.rs +++ b/src/rcu.rs @@ -327,14 +327,14 @@ macro_rules! bus_enable { impl Enable for crate::pac::$PER { #[inline(always)] fn enable(rcu: &mut Rcu) { - interrupt::free(|_| { + interrupt::free(|| { rcu.regs.$apben.modify(|_, w| w.$peren().set_bit()); }); } #[inline(always)] fn disable(rcu: &mut Rcu) { - interrupt::free(|_| { + interrupt::free(|| { rcu.regs.$apben.modify(|_, w| w.$peren().clear_bit()); }); } @@ -350,7 +350,7 @@ macro_rules! bus { impl Reset for crate::pac::$PER { #[inline(always)] fn reset(rcu: &mut Rcu) { - interrupt::free(|_| { + interrupt::free(|| { rcu.regs.$apbrst.modify(|_, w| w.$perrst().set_bit()); rcu.regs.$apbrst.modify(|_, w| w.$perrst().clear_bit()); });