From c31967e1b83f7b413ff295ee139edb07082fdbdf Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 07:45:10 +0200 Subject: [PATCH 1/7] Update PAC --- Cargo.toml | 3 +- src/eclic.rs | 107 ++++++++++++++++++++------------------------------- 2 files changed, 43 insertions(+), 67 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 158fc8f..0b5dc88 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -10,7 +10,8 @@ license = "ISC" edition = "2018" [dependencies] -gd32vf103-pac = "0.4.0" +# critical-section only required for doctests +gd32vf103-pac = { version = "0.5.0", features = ["critical-section"] } riscv = "0.6.0" nb = "0.1.2" void = { version = "1.0.2", default-features = false } diff --git a/src/eclic.rs b/src/eclic.rs index 071892c..20b3060 100644 --- a/src/eclic.rs +++ b/src/eclic.rs @@ -1,5 +1,4 @@ -use crate::pac::ECLIC; -use riscv::interrupt::Nr; +use crate::pac::{ECLIC, Interrupt}; const EFFECTIVE_LEVEL_PRIORITY_BITS: u8 = 4; @@ -84,43 +83,43 @@ pub trait EclicExt { fn get_priority_bits() -> u8; /// Setup `interrupt` - fn setup(interrupt: I, tt: TriggerType, level: Level, priority: Priority); + fn setup(interrupt: Interrupt, tt: TriggerType, level: Level, priority: Priority); /// Enables `interrupt` - unsafe fn unmask(interrupt: I); + unsafe fn unmask(interrupt: Interrupt); /// Disables `interrupt` - fn mask(interrupt: I); + fn mask(interrupt: Interrupt); /// Checks if `interrupt` is enabled - fn is_enabled(interrupt: I) -> bool; + fn is_enabled(interrupt: Interrupt) -> bool; /// Forces `interrupt` into pending state - fn pend(interrupt: I); + fn pend(interrupt: Interrupt); /// Clears `interrupt`'s pending state - fn unpend(interrupt: I); + fn unpend(interrupt: Interrupt); /// Checks if `interrupt` is pending - fn is_pending(interrupt: I) -> bool; + fn is_pending(interrupt: Interrupt) -> bool; /// Set `interrupt` trigger type - fn set_trigger_type(interrupt: I, tt: TriggerType); + fn set_trigger_type(interrupt: Interrupt, tt: TriggerType); /// Get `interrupt` trigger type - fn get_trigger_type(interrupt: I) -> Option; + fn get_trigger_type(interrupt: Interrupt) -> Option; // Set `interrupt` level - fn set_level(interrupt: I, level: Level); + fn set_level(interrupt: Interrupt, level: Level); // Get `interrupt` level - fn get_level(interrupt: I) -> Level; + fn get_level(interrupt: Interrupt) -> Level; // Set `interrupt` priority - fn set_priority(interrupt: I, priority: Priority); + fn set_priority(interrupt: Interrupt, priority: Priority); // Get `interrupt` interrupt - fn get_priority(interrupt: I) -> Priority; + fn get_priority(interrupt: Interrupt) -> Priority; } impl EclicExt for ECLIC { @@ -181,7 +180,7 @@ impl EclicExt for ECLIC { EFFECTIVE_LEVEL_PRIORITY_BITS - Self::get_level_bits() } - fn setup(interrupt: I, tt: TriggerType, level: Level, priority: Priority) { + fn setup(interrupt: Interrupt, tt: TriggerType, level: Level, priority: Priority) { Self::mask(interrupt); Self::set_trigger_type(interrupt, tt); Self::set_level(interrupt, level); @@ -190,31 +189,25 @@ impl EclicExt for ECLIC { } #[inline] - unsafe fn unmask(interrupt: I) { - let nr = usize::from(interrupt.nr()); - - (*Self::ptr()).clicints[nr] + unsafe fn unmask(interrupt: Interrupt) { + (*Self::ptr()).clicints[interrupt as usize] .clicintie .write(|w| w.ie().set_bit()) } #[inline] - fn mask(interrupt: I) { - let nr = usize::from(interrupt.nr()); - + fn mask(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintie .write(|w| w.ie().clear_bit()) } } #[inline] - fn is_enabled(interrupt: I) -> bool { - let nr = usize::from(interrupt.nr()); - + fn is_enabled(interrupt: Interrupt) -> bool { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintie .read() .ie() @@ -223,33 +216,27 @@ impl EclicExt for ECLIC { } #[inline] - fn pend(interrupt: I) { - let nr = usize::from(interrupt.nr()); - + fn pend(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintip .write(|w| w.ip().set_bit()) } } #[inline] - fn unpend(interrupt: I) { - let nr = usize::from(interrupt.nr()); - + fn unpend(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintip .write(|w| w.ip().clear_bit()) } } #[inline] - fn is_pending(interrupt: I) -> bool { - let nr = usize::from(interrupt.nr()); - + fn is_pending(interrupt: Interrupt) -> bool { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintip .read() .ip() @@ -258,21 +245,17 @@ impl EclicExt for ECLIC { } #[inline] - fn set_trigger_type(interrupt: I, tt: TriggerType) { - let nr = usize::from(interrupt.nr()); - + fn set_trigger_type(interrupt: Interrupt, tt: TriggerType) { unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintattr .write(|w| w.trig().bits(tt as u8).shv().clear_bit()) } } #[inline] - fn get_trigger_type(interrupt: I) -> Option { - let nr = usize::from(interrupt.nr()); - - match unsafe { (*Self::ptr()).clicints[nr].clicintattr.read().trig().bits() } { + fn get_trigger_type(interrupt: Interrupt) -> Option { + match unsafe { (*Self::ptr()).clicints[interrupt as usize].clicintattr.read().trig().bits() } { 0 => Some(TriggerType::Level), 1 => Some(TriggerType::RisingEdge), 3 => Some(TriggerType::FallingEdge), @@ -281,11 +264,9 @@ impl EclicExt for ECLIC { } #[inline] - fn set_level(interrupt: I, level: Level) { - let nr = usize::from(interrupt.nr()); - + fn set_level(interrupt: Interrupt, level: Level) { let mut intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() @@ -300,18 +281,16 @@ impl EclicExt for ECLIC { let level = level << (8 - level_bits); unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .write(|w| w.level_priority().bits(intctl | level)) } } #[inline] - fn get_level(interrupt: I) -> Level { - let nr = usize::from(interrupt.nr()); - + fn get_level(interrupt: Interrupt) -> Level { let intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() @@ -325,11 +304,9 @@ impl EclicExt for ECLIC { } #[inline] - fn set_priority(interrupt: I, priority: Priority) { - let nr = usize::from(interrupt.nr()); - + fn set_priority(interrupt: Interrupt, priority: Priority) { let mut intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() @@ -347,18 +324,16 @@ impl EclicExt for ECLIC { let priority = priority << (8 - EFFECTIVE_LEVEL_PRIORITY_BITS); unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .write(|w| w.level_priority().bits(intctl | priority)) } } #[inline] - fn get_priority(interrupt: I) -> Priority { - let nr = usize::from(interrupt.nr()); - + fn get_priority(interrupt: Interrupt) -> Priority { let intctl = unsafe { - (*Self::ptr()).clicints[nr] + (*Self::ptr()).clicints[interrupt as usize] .clicintctl .read() .level_priority() From d0530bea7f20493dbdfc65a84ed3e1070aa99643 Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 14:23:11 +0200 Subject: [PATCH 2/7] deps patch --- Cargo.toml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Cargo.toml b/Cargo.toml index 0b5dc88..f28d2f3 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -25,3 +25,5 @@ features = ["unproven"] [features] rt = ["gd32vf103-pac/rt"] +[patch.crates-io] +gd32vf103-pac = { path = "../gd32vf103-pac" } From 1bb7c3f2aeb37d57779dbcc1a4d63c6972232ee0 Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 14:26:57 +0200 Subject: [PATCH 3/7] field calls --- src/adc.rs | 122 +++++++++++++++++++++---------------------- src/afio.rs | 36 ++++++------- src/backup_domain.rs | 6 +-- src/delay.rs | 2 +- src/dma.rs | 4 +- src/eclic.rs | 16 +++--- src/exmc.rs | 8 +-- src/exti.rs | 32 ++++++------ src/gpio.rs | 12 ++--- src/i2c.rs | 92 ++++++++++++++++---------------- src/pwm.rs | 36 ++++++------- src/rcu.rs | 44 ++++++++-------- src/rtc.rs | 50 +++++++++--------- src/serial.rs | 40 +++++++------- src/spi.rs | 16 +++--- src/timer.rs | 28 +++++----- src/watchdog.rs | 20 +++---- 17 files changed, 282 insertions(+), 282 deletions(-) diff --git a/src/adc.rs b/src/adc.rs index 23634e5..a84177f 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -252,11 +252,11 @@ macro_rules! adc_hal { #[inline(always)] pub fn set_external_trigger(&mut self, trigger: ETSRC_A) { // Actually safe since the resulting u8 comes from our From<> impl - self.rb.ctl1.modify(|_, w| unsafe { w.etsrc().bits(trigger.into()) }) + self.rb.ctl1().modify(|_, w| unsafe { w.etsrc().bits(trigger.into()) }) } fn power_up(&mut self) { - self.rb.ctl1.modify(|_, w| w.adcon().set_bit()); + self.rb.ctl1().modify(|_, w| w.adcon().set_bit()); // The reference manual says that a stabilization time is needed after power_up, // this time can be found in the datasheets. @@ -266,7 +266,7 @@ macro_rules! adc_hal { } fn power_down(&mut self) { - self.rb.ctl1.modify(|_, w| w.adcon().clear_bit()); + self.rb.ctl1().modify(|_, w| w.adcon().clear_bit()); } fn reset(&mut self, rcu: &mut Rcu) { @@ -283,25 +283,25 @@ macro_rules! adc_hal { fn calibrate(&mut self) { // Reset calibration - self.rb.ctl1.modify(|_, w| w.rstclb().set_bit()); - while self.rb.ctl1.read().rstclb().bit_is_set() {} + self.rb.ctl1().modify(|_, w| w.rstclb().set_bit()); + while self.rb.ctl1().read().rstclb().bit_is_set() {} // Calibrate - self.rb.ctl1.modify(|_, w| w.clb().set_bit()); - while self.rb.ctl1.read().clb().bit_is_set() {} + self.rb.ctl1().modify(|_, w| w.clb().set_bit()); + while self.rb.ctl1().read().clb().bit_is_set() {} } fn setup_oneshot(&mut self) { - self.rb.ctl1.modify(|_, w| unsafe { w + self.rb.ctl1().modify(|_, w| unsafe { w .ctn().clear_bit() .eterc().set_bit() .etsrc().bits(0b111) }); - self.rb.ctl0.modify(|_, w| w + self.rb.ctl0().modify(|_, w| w .sm().clear_bit() .disrc().set_bit() ); - self.rb.rsq0.modify(|_, w| unsafe { w.rl().bits(0b0) }); + self.rb.rsq0().modify(|_, w| unsafe { w.rl().bits(0b0) }); } fn set_channel_sample_time(&mut self, chan: u8, sample_time: SampleTime) { @@ -310,24 +310,24 @@ macro_rules! adc_hal { // Safe because the value is controlled by our From for u8 unsafe { match chan { - 0 => self.rb.sampt1.modify(|_, w| w.spt0().bits(sample_time)), - 1 => self.rb.sampt1.modify(|_, w| w.spt1().bits(sample_time)), - 2 => self.rb.sampt1.modify(|_, w| w.spt2().bits(sample_time)), - 3 => self.rb.sampt1.modify(|_, w| w.spt3().bits(sample_time)), - 4 => self.rb.sampt1.modify(|_, w| w.spt4().bits(sample_time)), - 5 => self.rb.sampt1.modify(|_, w| w.spt5().bits(sample_time)), - 6 => self.rb.sampt1.modify(|_, w| w.spt6().bits(sample_time)), - 7 => self.rb.sampt1.modify(|_, w| w.spt7().bits(sample_time)), - 8 => self.rb.sampt1.modify(|_, w| w.spt8().bits(sample_time)), - 9 => self.rb.sampt1.modify(|_, w| w.spt9().bits(sample_time)), - 10 => self.rb.sampt0.modify(|_, w| w.spt10().bits(sample_time)), - 11 => self.rb.sampt0.modify(|_, w| w.spt11().bits(sample_time)), - 12 => self.rb.sampt0.modify(|_, w| w.spt12().bits(sample_time)), - 13 => self.rb.sampt0.modify(|_, w| w.spt13().bits(sample_time)), - 14 => self.rb.sampt0.modify(|_, w| w.spt14().bits(sample_time)), - 15 => self.rb.sampt0.modify(|_, w| w.spt15().bits(sample_time)), - 16 => self.rb.sampt0.modify(|_, w| w.spt16().bits(sample_time)), - 17 => self.rb.sampt0.modify(|_, w| w.spt17().bits(sample_time)), + 0 => self.rb.sampt1().modify(|_, w| w.spt0().bits(sample_time)), + 1 => self.rb.sampt1().modify(|_, w| w.spt1().bits(sample_time)), + 2 => self.rb.sampt1().modify(|_, w| w.spt2().bits(sample_time)), + 3 => self.rb.sampt1().modify(|_, w| w.spt3().bits(sample_time)), + 4 => self.rb.sampt1().modify(|_, w| w.spt4().bits(sample_time)), + 5 => self.rb.sampt1().modify(|_, w| w.spt5().bits(sample_time)), + 6 => self.rb.sampt1().modify(|_, w| w.spt6().bits(sample_time)), + 7 => self.rb.sampt1().modify(|_, w| w.spt7().bits(sample_time)), + 8 => self.rb.sampt1().modify(|_, w| w.spt8().bits(sample_time)), + 9 => self.rb.sampt1().modify(|_, w| w.spt9().bits(sample_time)), + 10 => self.rb.sampt0().modify(|_, w| w.spt10().bits(sample_time)), + 11 => self.rb.sampt0().modify(|_, w| w.spt11().bits(sample_time)), + 12 => self.rb.sampt0().modify(|_, w| w.spt12().bits(sample_time)), + 13 => self.rb.sampt0().modify(|_, w| w.spt13().bits(sample_time)), + 14 => self.rb.sampt0().modify(|_, w| w.spt14().bits(sample_time)), + 15 => self.rb.sampt0().modify(|_, w| w.spt15().bits(sample_time)), + 16 => self.rb.sampt0().modify(|_, w| w.spt16().bits(sample_time)), + 17 => self.rb.sampt0().modify(|_, w| w.spt17().bits(sample_time)), _ => unreachable!(), } } @@ -338,28 +338,28 @@ macro_rules! adc_hal { let bits = channels.iter().take(6).enumerate().fold(0u32, |s, (i, c)| s | ((*c as u32) << (i * 5)) ); - self.rb.rsq2.write(|w| unsafe { w.bits(bits) }); + self.rb.rsq2().write(|w| unsafe { w.bits(bits) }); if len > 6 { let bits = channels.iter().skip(6).take(6).enumerate().fold(0u32, |s, (i, c)| s | ((*c as u32) << (i * 5)) ); - self.rb.rsq1.write(|w| unsafe { w.bits(bits) }); + self.rb.rsq1().write(|w| unsafe { w.bits(bits) }); } if len > 12 { let bits = channels.iter().skip(12).take(4).enumerate().fold(0u32, |s, (i, c)| s | ((*c as u32) << (i * 5)) ); - self.rb.rsq0.write(|w| unsafe { w.bits(bits) }); + self.rb.rsq0().write(|w| unsafe { w.bits(bits) }); } - self.rb.rsq0.modify(|_, w| unsafe { w.rl().bits((len-1) as u8) }); + self.rb.rsq0().modify(|_, w| unsafe { w.rl().bits((len-1) as u8) }); } fn set_continuous_mode(&mut self, continuous: bool) { - self.rb.ctl1.modify(|_, w| w.ctn().bit(continuous)); + self.rb.ctl1().modify(|_, w| w.ctn().bit(continuous)); } fn set_discontinuous_mode(&mut self, channels_count: Option) { - self.rb.ctl0.modify(|_, w| match channels_count { + self.rb.ctl0().modify(|_, w| match channels_count { Some(count) => unsafe { w.disrc().set_bit().disnum().bits(count) }, None => w.disrc().clear_bit(), }) @@ -380,22 +380,22 @@ macro_rules! adc_hal { // Dummy read in case something accidentally triggered // a conversion by writing to CTL1 without changing any // of the bits - self.rb.rdata.read().rdata().bits(); + self.rb.rdata().read().rdata().bits(); self.set_channel_sample_time(chan, self.sample_time); - self.rb.rsq2.modify(|_, w| unsafe { w.rsq0().bits(chan) }); + self.rb.rsq2().modify(|_, w| unsafe { w.rsq0().bits(chan) }); // ADC start conversion of regular sequence - self.rb.ctl1.modify(|_, w| + self.rb.ctl1().modify(|_, w| w .swrcst().set_bit() .dal().bit(self.align.into()) ); - while self.rb.ctl1.read().swrcst().bit_is_set() {} + while self.rb.ctl1().read().swrcst().bit_is_set() {} // ADC wait for conversion results - while self.rb.stat.read().eoc().bit_is_clear() {} + while self.rb.stat().read().eoc().bit_is_clear() {} - let res = self.rb.rdata.read().rdata().bits(); + let res = self.rb.rdata().read().rdata().bits(); res } @@ -445,8 +445,8 @@ adc_hal!(ADC0: adc0, ADC1: adc1); impl Adc { fn read_aux(&mut self, chan: u8) -> u16 { - let tsv_off = if self.rb.ctl1.read().tsvren().bit_is_clear() { - self.rb.ctl1.modify(|_, w| w.tsvren().set_bit()); + let tsv_off = if self.rb.ctl1().read().tsvren().bit_is_clear() { + self.rb.ctl1().modify(|_, w| w.tsvren().set_bit()); // The reference manual says that a stabilization time is needed after the powering the // sensor, this time can be found in the datasheets. @@ -461,7 +461,7 @@ impl Adc { let val = self.convert(chan); if tsv_off { - self.rb.ctl1.modify(|_, w| w.tsvren().clear_bit()); + self.rb.ctl1().modify(|_, w| w.tsvren().clear_bit()); } val @@ -592,19 +592,19 @@ impl Receive for AdcDma { impl TransferPayload for AdcDma { fn start(&mut self) { self.channel.start(); - self.payload.adc.rb.ctl1.modify(|_, w| w.ctn().set_bit()); - self.payload.adc.rb.ctl1.modify(|_, w| w.adcon().set_bit()); + self.payload.adc.rb.ctl1().modify(|_, w| w.ctn().set_bit()); + self.payload.adc.rb.ctl1().modify(|_, w| w.adcon().set_bit()); } fn stop(&mut self) { self.channel.stop(); - self.payload.adc.rb.ctl1.modify(|_, w| w.ctn().clear_bit()); + self.payload.adc.rb.ctl1().modify(|_, w| w.ctn().clear_bit()); } } impl TransferPayload for AdcDma { fn start(&mut self) { self.channel.start(); - self.payload.adc.rb.ctl1.modify(|_, w| w.adcon().set_bit()); + self.payload.adc.rb.ctl1().modify(|_, w| w.adcon().set_bit()); } fn stop(&mut self) { self.channel.stop(); @@ -616,11 +616,11 @@ impl Adc { where PIN: Channel, { - self.rb.ctl0.modify(|_, w| w.disrc().clear_bit()); - self.rb.ctl1.modify(|_, w| w.dal().bit(self.align.into())); + self.rb.ctl0().modify(|_, w| w.disrc().clear_bit()); + self.rb.ctl1().modify(|_, w| w.dal().bit(self.align.into())); self.set_channel_sample_time(PIN::channel(), self.sample_time); - self.rb.rsq2.modify(|_, w| unsafe { w.rsq0().bits(PIN::channel()) }); - self.rb.ctl1.modify(|_, w| w.dma().set_bit()); + self.rb.rsq2().modify(|_, w| unsafe { w.rsq0().bits(PIN::channel()) }); + self.rb.ctl1().modify(|_, w| w.dma().set_bit()); RxDma { payload: AdcPayload { adc: self, pins, _mode: PhantomData }, channel: dma_ch } } @@ -629,16 +629,16 @@ impl Adc { where Self: SetChannels, { - self.rb.ctl1.modify(|_, w| w + self.rb.ctl1().modify(|_, w| w .adcon().clear_bit() .dma().clear_bit() .ctn().clear_bit() .dal().bit(self.align.into()) ); - self.rb.ctl0.modify(|_, w| w.sm().set_bit().disrc().clear_bit()); + self.rb.ctl0().modify(|_, w| w.sm().set_bit().disrc().clear_bit()); self.set_samples(); self.set_sequence(); - self.rb.ctl1.modify(|_, w| w.dma().set_bit().adcon().set_bit()); + self.rb.ctl1().modify(|_, w| w.dma().set_bit().adcon().set_bit()); RxDma { payload: AdcPayload { adc: self, pins, _mode: PhantomData }, channel: dma_ch } } @@ -652,8 +652,8 @@ where self.stop(); let AdcDma { payload, channel } = self; - payload.adc.rb.ctl1.modify(|_, w| w.dma().clear_bit()); - payload.adc.rb.ctl0.modify(|_, w| w.disrc().set_bit()); + payload.adc.rb.ctl1().modify(|_, w| w.dma().clear_bit()); + payload.adc.rb.ctl0().modify(|_, w| w.disrc().set_bit()); (payload.adc, payload.pins, channel) } @@ -667,9 +667,9 @@ where self.stop(); let AdcDma { payload, channel } = self; - payload.adc.rb.ctl1.modify(|_, w| w.dma().clear_bit()); - payload.adc.rb.ctl0.modify(|_, w| w.disrc().set_bit()); - payload.adc.rb.ctl0.modify(|_, w| w.sm().clear_bit()); + payload.adc.rb.ctl1().modify(|_, w| w.dma().clear_bit()); + payload.adc.rb.ctl0().modify(|_, w| w.disrc().set_bit()); + payload.adc.rb.ctl0().modify(|_, w| w.sm().clear_bit()); (payload.adc, payload.pins, channel) } @@ -686,7 +686,7 @@ where // the transfer let (ptr, len) = unsafe { buffer.static_write_buffer() }; unsafe { - self.channel.set_peripheral_address(&(*ADC0::ptr()).rdata as *const _ as u32, false); + self.channel.set_peripheral_address(&(*ADC0::ptr()).rdata() as *const _ as u32, false); self.channel.set_memory_address(ptr as u32, true); } self.channel.set_transfer_length(len); @@ -716,7 +716,7 @@ where // until the end of the transfer. let (ptr, len) = unsafe { buffer.static_write_buffer() }; unsafe { - self.channel.set_peripheral_address(&(*ADC0::ptr()).rdata as *const _ as u32, false); + self.channel.set_peripheral_address(&(*ADC0::ptr()).rdata() as *const _ as u32, false); self.channel.set_memory_address(ptr as u32, true); } self.channel.set_transfer_length(len); diff --git a/src/afio.rs b/src/afio.rs index e2ca140..be3cead 100644 --- a/src/afio.rs +++ b/src/afio.rs @@ -40,7 +40,7 @@ impl Afio { PB4>, ) { // Set remap to "JTAG-DP Disabled" - self.afio.pcf0.modify(|_, w| unsafe { + self.afio.pcf0().modify(|_, w| unsafe { w.swj_cfg().bits(0b100) }); @@ -59,22 +59,22 @@ impl Afio { #[inline] pub fn extiss(&mut self, port: Port, pin: u8) { match pin { - 0 => self.afio.extiss0.modify(|_, w| unsafe { w.exti0_ss().bits(port as u8)}), - 1 => self.afio.extiss0.modify(|_, w| unsafe { w.exti1_ss().bits(port as u8)}), - 2 => self.afio.extiss0.modify(|_, w| unsafe { w.exti2_ss().bits(port as u8)}), - 3 => self.afio.extiss0.modify(|_, w| unsafe { w.exti3_ss().bits(port as u8)}), - 4 => self.afio.extiss1.modify(|_, w| unsafe { w.exti4_ss().bits(port as u8)}), - 5 => self.afio.extiss1.modify(|_, w| unsafe { w.exti5_ss().bits(port as u8)}), - 6 => self.afio.extiss1.modify(|_, w| unsafe { w.exti6_ss().bits(port as u8)}), - 7 => self.afio.extiss1.modify(|_, w| unsafe { w.exti7_ss().bits(port as u8)}), - 8 => self.afio.extiss2.modify(|_, w| unsafe { w.exti8_ss().bits(port as u8)}), - 9 => self.afio.extiss2.modify(|_, w| unsafe { w.exti9_ss().bits(port as u8)}), - 10 => self.afio.extiss2.modify(|_, w| unsafe { w.exti10_ss().bits(port as u8)}), - 11 => self.afio.extiss2.modify(|_, w| unsafe { w.exti11_ss().bits(port as u8)}), - 12 => self.afio.extiss3.modify(|_, w| unsafe { w.exti12_ss().bits(port as u8)}), - 13 => self.afio.extiss3.modify(|_, w| unsafe { w.exti13_ss().bits(port as u8)}), - 14 => self.afio.extiss3.modify(|_, w| unsafe { w.exti14_ss().bits(port as u8)}), - 15 => self.afio.extiss3.modify(|_, w| unsafe { w.exti15_ss().bits(port as u8)}), + 0 => self.afio.extiss0().modify(|_, w| unsafe { w.exti0_ss().bits(port as u8)}), + 1 => self.afio.extiss0().modify(|_, w| unsafe { w.exti1_ss().bits(port as u8)}), + 2 => self.afio.extiss0().modify(|_, w| unsafe { w.exti2_ss().bits(port as u8)}), + 3 => self.afio.extiss0().modify(|_, w| unsafe { w.exti3_ss().bits(port as u8)}), + 4 => self.afio.extiss1().modify(|_, w| unsafe { w.exti4_ss().bits(port as u8)}), + 5 => self.afio.extiss1().modify(|_, w| unsafe { w.exti5_ss().bits(port as u8)}), + 6 => self.afio.extiss1().modify(|_, w| unsafe { w.exti6_ss().bits(port as u8)}), + 7 => self.afio.extiss1().modify(|_, w| unsafe { w.exti7_ss().bits(port as u8)}), + 8 => self.afio.extiss2().modify(|_, w| unsafe { w.exti8_ss().bits(port as u8)}), + 9 => self.afio.extiss2().modify(|_, w| unsafe { w.exti9_ss().bits(port as u8)}), + 10 => self.afio.extiss2().modify(|_, w| unsafe { w.exti10_ss().bits(port as u8)}), + 11 => self.afio.extiss2().modify(|_, w| unsafe { w.exti11_ss().bits(port as u8)}), + 12 => self.afio.extiss3().modify(|_, w| unsafe { w.exti12_ss().bits(port as u8)}), + 13 => self.afio.extiss3().modify(|_, w| unsafe { w.exti13_ss().bits(port as u8)}), + 14 => self.afio.extiss3().modify(|_, w| unsafe { w.exti14_ss().bits(port as u8)}), + 15 => self.afio.extiss3().modify(|_, w| unsafe { w.exti15_ss().bits(port as u8)}), _ => {} } } @@ -110,7 +110,7 @@ macro_rules! remap { #[inline(always)] fn remap(afio: &mut Afio, variant: $variant) { - let pcf0 = &afio.afio.pcf0; + let pcf0 = &afio.afio.pcf0(); remap_set!(pcf0, $field, $variant, variant); } } diff --git a/src/backup_domain.rs b/src/backup_domain.rs index 363f757..93a6a60 100644 --- a/src/backup_domain.rs +++ b/src/backup_domain.rs @@ -25,7 +25,7 @@ impl BkpExt for BKP { PMU::enable(rcu); // Enable access to the backup registers - pmu.ctl.modify(|_r, w| w.bkpwen().set_bit()); + pmu.ctl().modify(|_r, w| w.bkpwen().set_bit()); BackupDomain { _regs: self } @@ -51,11 +51,11 @@ impl Lxtal { /// Enable and don't wait for stabilization. fn just_enable(rcu: &rcu::RegisterBlock) { // Enable LXTAL - rcu.bdctl + rcu.bdctl() .modify(|_, w| w.lxtalen().set_bit().lxtalbps().clear_bit()); } fn is_stable(rcu: &rcu::RegisterBlock) -> bool { - rcu.bdctl.read().lxtalstb().bit() + rcu.bdctl().read().lxtalstb().bit() } /// Enable the clock and block until stabilized. pub fn enable_block(rcu: &Rcu) -> Self { diff --git a/src/delay.rs b/src/delay.rs index eb65ec0..b7aae0a 100644 --- a/src/delay.rs +++ b/src/delay.rs @@ -135,7 +135,7 @@ macro_rules! delay { let freq = 1_000_000 / us; self.timer.start(freq.hz()); while let Err(_) = self.timer.wait() { } - self.timer.tim.ctl0.modify(|_, w| w.cen().clear_bit()); + self.timer.tim.ctl0().modify(|_, w| w.cen().clear_bit()); } } diff --git a/src/dma.rs b/src/dma.rs index 8c1a2f8..9037a3c 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -231,7 +231,7 @@ macro_rules! dma { pub fn intf(&self) -> $dmaX::intf::R { // NOTE(unsafe) atomic read with no side effects - unsafe { (*$DMAX::ptr()).intf.read() } + unsafe { (*$DMAX::ptr()).intf().read() } } pub fn intc(&self) -> &$dmaX::INTC { @@ -433,7 +433,7 @@ macro_rules! dma { // reset the DMA control registers (stops all on-going transfers) $( - self.$ctlX.reset(); + self.$ctlX().reset(); )+ Channels((), $($CX { _0: () }),+) diff --git a/src/eclic.rs b/src/eclic.rs index 20b3060..e4a73be 100644 --- a/src/eclic.rs +++ b/src/eclic.rs @@ -126,10 +126,10 @@ impl EclicExt for ECLIC { fn reset() { let eclic = unsafe { &*Self::ptr() }; - eclic.cliccfg.write(|w| unsafe { w.bits(0) }); - eclic.mth.write(|w| unsafe { w.bits(0) }); + eclic.cliccfg().write(|w| unsafe { w.bits(0) }); + eclic.mth().write(|w| unsafe { w.bits(0) }); - for nr in 0..eclic.clicinfo.read().num_interrupt().bits() as usize { + for nr in 0..eclic.clicinfo().read().num_interrupt().bits() as usize { eclic.clicints[nr].clicintip.write(|w| unsafe { w.bits(0) }); eclic.clicints[nr].clicintie.write(|w| unsafe { w.bits(0) }); eclic.clicints[nr] @@ -143,22 +143,22 @@ impl EclicExt for ECLIC { #[inline] fn set_threshold_level(level: Level) { - unsafe { (*Self::ptr()).mth.write(|w| w.mth().bits(level as u8)) } + unsafe { (*Self::ptr()).mth().write(|w| w.mth().bits(level as u8)) } } #[inline] fn get_threshold_level() -> Level { - unsafe { core::mem::transmute((*Self::ptr()).mth.read().mth().bits() & 0xF) } + unsafe { core::mem::transmute((*Self::ptr()).mth().read().mth().bits() & 0xF) } } #[inline] fn set_level_priority_bits(lp: LevelPriorityBits) { - unsafe { (*Self::ptr()).cliccfg.write(|w| w.nlbits().bits(lp as u8)) } + unsafe { (*Self::ptr()).cliccfg().write(|w| w.nlbits().bits(lp as u8)) } } #[inline] fn get_level_priority_bits() -> Option { - match unsafe { (*Self::ptr()).cliccfg.read().nlbits().bits() } { + match unsafe { (*Self::ptr()).cliccfg().read().nlbits().bits() } { 0 => Some(LevelPriorityBits::L0P4), 1 => Some(LevelPriorityBits::L1P3), 2 => Some(LevelPriorityBits::L2P2), @@ -170,7 +170,7 @@ impl EclicExt for ECLIC { #[inline] fn get_level_bits() -> u8 { - let bits = unsafe { (*Self::ptr()).cliccfg.read().nlbits().bits() }; + let bits = unsafe { (*Self::ptr()).cliccfg().read().nlbits().bits() }; core::cmp::min(bits, EFFECTIVE_LEVEL_PRIORITY_BITS) } diff --git a/src/exmc.rs b/src/exmc.rs index 90cbc59..0a61395 100644 --- a/src/exmc.rs +++ b/src/exmc.rs @@ -32,7 +32,7 @@ impl Exmc { pub fn new(regs: EXMC, pins: ExmcPins, conf: ExmcConfiguration, timing_conf: ExmcTimingConfiguration, rcu: &mut Rcu) -> Self { EXMC::enable(rcu); - regs.snctl0.write(|w| unsafe { + regs.snctl0().write(|w| unsafe { w.nrmux().bit(conf.address_data_mux_enabled); w.nrtp().bits(conf.memory_type as u8); w.nrw().bits(conf.databus_width as u8); @@ -44,7 +44,7 @@ impl Exmc { w }); - regs.sntcfg0.write(|w| unsafe { + regs.sntcfg0().write(|w| unsafe { w.aset().bits(timing_conf.address_setup_time); w.ahld().bits(timing_conf.address_hold_time); w.dset().bits(timing_conf.data_setup_time); @@ -52,7 +52,7 @@ impl Exmc { }); // Enable memory bank - regs.snctl0.modify(|_, w| w.nrbken().set_bit()); + regs.snctl0().modify(|_, w| w.nrbken().set_bit()); Exmc { regs, @@ -62,7 +62,7 @@ impl Exmc { pub fn release(self) -> (EXMC, ExmcPins) { // Disable memory bank - self.regs.snctl0.modify(|_, w| w.nrbken().clear_bit()); + self.regs.snctl0().modify(|_, w| w.nrbken().clear_bit()); (self.regs, self.pins) } diff --git a/src/exti.rs b/src/exti.rs index 51a0c6f..fb501e7 100644 --- a/src/exti.rs +++ b/src/exti.rs @@ -83,20 +83,20 @@ impl Exti { unsafe { match edge { TriggerEdge::Falling => { - self.raw.ften.modify(|r, w| w.bits(r.bits() | bm)); - self.raw.rten.modify(|r, w| w.bits(r.bits() & !bm)); + self.raw.ften().modify(|r, w| w.bits(r.bits() | bm)); + self.raw.rten().modify(|r, w| w.bits(r.bits() & !bm)); }, TriggerEdge::Rising => { - self.raw.ften.modify(|r, w| w.bits(r.bits() & !bm)); - self.raw.rten.modify(|r, w| w.bits(r.bits() | bm)); + self.raw.ften().modify(|r, w| w.bits(r.bits() & !bm)); + self.raw.rten().modify(|r, w| w.bits(r.bits() | bm)); }, TriggerEdge::Both => { - self.raw.ften.modify(|r, w| w.bits(r.bits() | bm)); - self.raw.rten.modify(|r, w| w.bits(r.bits() | bm)); + self.raw.ften().modify(|r, w| w.bits(r.bits() | bm)); + self.raw.rten().modify(|r, w| w.bits(r.bits() | bm)); } } - self.raw.inten.modify(|r, w| w.bits(r.bits() | bm)); + self.raw.inten().modify(|r, w| w.bits(r.bits() | bm)); } } @@ -106,9 +106,9 @@ impl Exti { let bm: u32 = 1 << line.0; unsafe { - self.raw.rten.modify(|r, w| w.bits(r.bits() & !bm)); - self.raw.ften.modify(|r, w| w.bits(r.bits() & !bm)); - self.raw.inten.modify(|r, w| w.bits(r.bits() & !bm)); + self.raw.rten().modify(|r, w| w.bits(r.bits() & !bm)); + self.raw.ften().modify(|r, w| w.bits(r.bits() & !bm)); + self.raw.inten().modify(|r, w| w.bits(r.bits() & !bm)); } } @@ -118,9 +118,9 @@ impl Exti { let bm: u32 = 1 << line.0; if let ExtiEvent::Enable = enable { - unsafe { (*EXTI::ptr()).even.modify(|r, w| w.bits(r.bits() | bm)) }; + unsafe { (*EXTI::ptr()).even().modify(|r, w| w.bits(r.bits() | bm)) }; } else { - unsafe { (*EXTI::ptr()).even.modify(|r, w| w.bits(r.bits() & !bm)) }; + unsafe { (*EXTI::ptr()).even().modify(|r, w| w.bits(r.bits() & !bm)) }; } } @@ -128,27 +128,27 @@ impl Exti { #[inline] pub fn is_pending(line: ExtiLine) -> bool { let bm: u32 = 1 << line.0; - unsafe { (*EXTI::ptr()).pd.read().bits() & bm != 0 } + unsafe { (*EXTI::ptr()).pd().read().bits() & bm != 0 } } /// Clear the pending interrupt flag #[inline] pub fn clear(line: ExtiLine) { let bm: u32 = 1 << line.0; - unsafe { (*EXTI::ptr()).pd.write(|w| w.bits(bm)) }; + unsafe { (*EXTI::ptr()).pd().write(|w| w.bits(bm)) }; } /// Request a pending interrupt for this line from software #[inline] pub fn pend(line: ExtiLine) { let bm: u32 = 1 << line.0; - unsafe { (*EXTI::ptr()).swiev.modify(|r, w| w.bits(r.bits() | bm)) }; + unsafe { (*EXTI::ptr()).swiev().modify(|r, w| w.bits(r.bits() | bm)) }; } /// Deactivate a software pending request for this line #[inline] pub fn unpend(line: ExtiLine) { let bm: u32 = 1 << line.0; - unsafe { (*EXTI::ptr()).swiev.modify(|r, w| w.bits(r.bits() & !bm)) }; + unsafe { (*EXTI::ptr()).swiev().modify(|r, w| w.bits(r.bits() & !bm)) }; } } diff --git a/src/gpio.rs b/src/gpio.rs index 8cced3c..6678911 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -119,11 +119,11 @@ trait PeripheralAccess { interrupt::free(|_| { if index < 8 { - regs.ctl0.modify(|r, w| unsafe { + regs.ctl0().modify(|r, w| unsafe { w.bits((r.bits() & mask) | value) }); } else { - regs.ctl1.modify(|r, w| unsafe { + regs.ctl1().modify(|r, w| unsafe { w.bits((r.bits() & mask) | value) }); } @@ -137,7 +137,7 @@ trait PeripheralAccess { let regs = Self::peripheral(); // NOTE(unsafe) atomic write to a stateless register - regs.bop.write(|w| unsafe { w.bits(1u32 << index) }); + regs.bop().write(|w| unsafe { w.bits(1u32 << index) }); } #[inline(always)] @@ -147,7 +147,7 @@ trait PeripheralAccess { let regs = Self::peripheral(); // NOTE(unsafe) atomic write to a stateless register - regs.bop.write(|w| unsafe { w.bits(1u32 << (16 + index)) }); + regs.bop().write(|w| unsafe { w.bits(1u32 << (16 + index)) }); } #[inline(always)] @@ -157,7 +157,7 @@ trait PeripheralAccess { let regs = Self::peripheral(); let mask = 1u32 << index; - regs.istat.read().bits() & mask != 0 + regs.istat().read().bits() & mask != 0 } #[inline(always)] @@ -167,7 +167,7 @@ trait PeripheralAccess { let regs = Self::peripheral(); let mask = 1u32 << index; - regs.octl.read().bits() & mask != 0 + regs.octl().read().bits() & mask != 0 } } diff --git a/src/i2c.rs b/src/i2c.rs index bf7e10b..115faeb 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -225,19 +225,19 @@ fn blocking_i2c( macro_rules! wait_for_flag { ($i2c:expr, $flag:ident) => {{ - let stat0 = $i2c.stat0.read(); + let stat0 = $i2c.stat0().read(); if stat0.berr().bit_is_set() { - $i2c.stat0.modify(|_, w| w.berr().clear_bit()); + $i2c.stat0().modify(|_, w| w.berr().clear_bit()); Err(Other(Error::Bus)) } else if stat0.lostarb().bit_is_set() { - $i2c.stat0.modify(|_, w| w.lostarb().clear_bit()); + $i2c.stat0().modify(|_, w| w.lostarb().clear_bit()); Err(Other(Error::Arbitration)) } else if stat0.aerr().bit_is_set() { - $i2c.stat0.modify(|_, w| w.aerr().clear_bit()); + $i2c.stat0().modify(|_, w| w.aerr().clear_bit()); Err(Other(Error::Acknowledge)) } else if stat0.ouerr().bit_is_set() { - $i2c.stat0.modify(|_, w| w.ouerr().clear_bit()); + $i2c.stat0().modify(|_, w| w.ouerr().clear_bit()); Err(Other(Error::Overrun)) } else if stat0.$flag().bit_is_set() { Ok(()) @@ -301,17 +301,17 @@ macro_rules! hal { let freq = self.mode.get_frequency(); let pclk1_mhz = (self.pclk1 / 1000000) as u16; - self.i2c.ctl1.write(|w| unsafe { + self.i2c.ctl1().write(|w| unsafe { w.i2cclk().bits(pclk1_mhz as u8) }); - self.i2c.ctl0.write(|w| w.i2cen().clear_bit()); + self.i2c.ctl0().write(|w| w.i2cen().clear_bit()); match self.mode { Mode::Standard { .. } => { - self.i2c.rt.write(|w| unsafe { + self.i2c.rt().write(|w| unsafe { w.risetime().bits((pclk1_mhz + 1) as u8) }); - self.i2c.ckcfg.write(|w| unsafe { + self.i2c.ckcfg().write(|w| unsafe { w.clkc().bits(((self.pclk1 / (freq.0 * 2)) as u16).max(4)) }); }, @@ -321,19 +321,19 @@ macro_rules! hal { Mode::FastPlus { ref duty_cycle, .. } => { self.configure_fast_mode(pclk1_mhz, freq, duty_cycle); - self.i2c.fmpcfg.write(|w| w.fmpen().set_bit()) + self.i2c.fmpcfg().write(|w| w.fmpen().set_bit()) } }; - self.i2c.ctl0.modify(|_, w| w.i2cen().set_bit()); + self.i2c.ctl0().modify(|_, w| w.i2cen().set_bit()); } fn configure_fast_mode(&self, pclk1_mhz: u16, freq: Hertz, duty_cycle: &DutyCycle) { - self.i2c.rt.write(|w| unsafe { + self.i2c.rt().write(|w| unsafe { w.risetime().bits((pclk1_mhz * 300 / 1000 + 1) as u8) }); - self.i2c.ckcfg.write(|w| { + self.i2c.ckcfg().write(|w| { let (freq, duty) = match duty_cycle { DutyCycle::Ratio2to1 => (((self.pclk1 / (freq.0 * 3)) as u16).max(1), false), DutyCycle::Ratio16to9 => (((self.pclk1 / (freq.0 * 25)) as u16).max(1), true) @@ -347,14 +347,14 @@ macro_rules! hal { /// Perform an I2C software reset fn reset(&mut self) { - self.i2c.ctl0.write(|w| w.i2cen().set_bit().sreset().set_bit()); - self.i2c.ctl0.reset(); + self.i2c.ctl0().write(|w| w.i2cen().set_bit().sreset().set_bit()); + self.i2c.ctl0().reset(); self.init(); } /// Generate START condition fn send_start(&mut self) { - self.i2c.ctl0.modify(|_, w| w.start().set_bit()); + self.i2c.ctl0().modify(|_, w| w.start().set_bit()); } /// Check if START condition is generated. If the condition is not generated, this @@ -368,7 +368,7 @@ macro_rules! hal { /// method returns `WouldBlock` so the program can act accordingly /// (busy wait, async, ...) fn wait_for_stop(&mut self) -> NbResult<(), Error> { - if self.i2c.ctl0.read().stop().bit_is_set() { + if self.i2c.ctl0().read().stop().bit_is_set() { Ok(()) } else { Err(WouldBlock) @@ -378,12 +378,12 @@ macro_rules! hal { /// Sends the (7-Bit) address on the I2C bus. The 8th bit on the bus is set /// depending on wether it is a read or write transfer. fn send_addr(&self, addr: u8, read: bool) { - self.i2c.data.write(|w| unsafe { w.trb().bits(addr << 1 | (if read {1} else {0})) }); + self.i2c.data().write(|w| unsafe { w.trb().bits(addr << 1 | (if read {1} else {0})) }); } /// Generate STOP condition fn send_stop(&self) { - self.i2c.ctl0.modify(|_, w| w.stop().set_bit()); + self.i2c.ctl0().modify(|_, w| w.stop().set_bit()); } /// Releases the I2C peripheral and associated pins @@ -425,7 +425,7 @@ macro_rules! hal { } fn send_addr_and_wait(&mut self, addr: u8, read: bool) -> NbResult<(), Error> { - self.nb.i2c.stat0.read(); + self.nb.i2c.stat0().read(); self.nb.send_addr(addr, read); let ret = busy_wait_cycles!(wait_for_flag!(self.nb.i2c, addsend), self.addr_timeout); @@ -436,14 +436,14 @@ macro_rules! hal { } fn write_bytes_and_wait(&mut self, bytes: &[u8]) -> NbResult<(), Error> { - self.nb.i2c.stat0.read(); - self.nb.i2c.stat1.read(); + self.nb.i2c.stat0().read(); + self.nb.i2c.stat1().read(); - self.nb.i2c.data.write(|w| unsafe { w.trb().bits(bytes[0]) }); + self.nb.i2c.data().write(|w| unsafe { w.trb().bits(bytes[0]) }); for byte in &bytes[1..] { busy_wait_cycles!(wait_for_flag!(self.nb.i2c, tbe), self.data_timeout)?; - self.nb.i2c.data.write(|w| unsafe { w.trb().bits(*byte) }); + self.nb.i2c.data().write(|w| unsafe { w.trb().bits(*byte) }); } busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btc), self.data_timeout)?; @@ -483,53 +483,53 @@ macro_rules! hal { match buffer.len() { 1 => { - self.nb.i2c.ctl0.modify(|_, w| w.acken().clear_bit()); - self.nb.i2c.stat0.read(); - self.nb.i2c.stat1.read(); + self.nb.i2c.ctl0().modify(|_, w| w.acken().clear_bit()); + self.nb.i2c.stat0().read(); + self.nb.i2c.stat1().read(); self.nb.send_stop(); busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rbne), self.data_timeout)?; - buffer[0] = self.nb.i2c.data.read().trb().bits(); + buffer[0] = self.nb.i2c.data().read().trb().bits(); busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?; - self.nb.i2c.ctl0.modify(|_, w| w.acken().set_bit()); + self.nb.i2c.ctl0().modify(|_, w| w.acken().set_bit()); } 2 => { - self.nb.i2c.ctl0.modify(|_, w| w.pecen().set_bit().acken().set_bit()); - self.nb.i2c.stat0.read(); - self.nb.i2c.stat1.read(); - self.nb.i2c.ctl0.modify(|_, w| w.acken().clear_bit()); + self.nb.i2c.ctl0().modify(|_, w| w.pecen().set_bit().acken().set_bit()); + self.nb.i2c.stat0().read(); + self.nb.i2c.stat1().read(); + self.nb.i2c.ctl0().modify(|_, w| w.acken().clear_bit()); busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btc), self.data_timeout)?; self.nb.send_stop(); - buffer[0] = self.nb.i2c.data.read().trb().bits(); - buffer[1] = self.nb.i2c.data.read().trb().bits(); + buffer[0] = self.nb.i2c.data().read().trb().bits(); + buffer[1] = self.nb.i2c.data().read().trb().bits(); busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?; - self.nb.i2c.ctl0.modify(|_, w| w.pecen().clear_bit().acken().clear_bit()); - self.nb.i2c.ctl0.modify(|_, w| w.acken().set_bit()); + self.nb.i2c.ctl0().modify(|_, w| w.pecen().clear_bit().acken().clear_bit()); + self.nb.i2c.ctl0().modify(|_, w| w.acken().set_bit()); } buffer_len => { - self.nb.i2c.ctl0.modify(|_, w| w.acken().set_bit()); - self.nb.i2c.stat0.read(); - self.nb.i2c.stat1.read(); + self.nb.i2c.ctl0().modify(|_, w| w.acken().set_bit()); + self.nb.i2c.stat0().read(); + self.nb.i2c.stat1().read(); let (first_bytes, last_two_bytes) = buffer.split_at_mut(buffer_len - 3); for byte in first_bytes { busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rbne), self.data_timeout)?; - *byte = self.nb.i2c.data.read().trb().bits(); + *byte = self.nb.i2c.data().read().trb().bits(); } busy_wait_cycles!(wait_for_flag!(self.nb.i2c, btc), self.data_timeout)?; - self.nb.i2c.ctl0.modify(|_, w| w.acken().clear_bit()); - last_two_bytes[0] = self.nb.i2c.data.read().trb().bits(); + self.nb.i2c.ctl0().modify(|_, w| w.acken().clear_bit()); + last_two_bytes[0] = self.nb.i2c.data().read().trb().bits(); self.nb.send_stop(); - last_two_bytes[1] = self.nb.i2c.data.read().trb().bits(); + last_two_bytes[1] = self.nb.i2c.data().read().trb().bits(); busy_wait_cycles!(wait_for_flag!(self.nb.i2c, rbne), self.data_timeout)?; - last_two_bytes[2] = self.nb.i2c.data.read().trb().bits(); + last_two_bytes[2] = self.nb.i2c.data().read().trb().bits(); busy_wait_cycles!(self.nb.wait_for_stop(), self.data_timeout)?; - self.nb.i2c.ctl0.modify(|_, w| w.acken().set_bit()); + self.nb.i2c.ctl0().modify(|_, w| w.acken().set_bit()); } } diff --git a/src/pwm.rs b/src/pwm.rs index d3430ed..6ae7e20 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -191,7 +191,7 @@ macro_rules! advanced_pwm_timer { /* Advanced TIMER implements a BREAK function that deactivates * the outputs. This bit automatically activates the output when * no break input is present */ - timer.cchp.modify(|_, w| w.oaen().set_bit()); + timer.cchp().modify(|_, w| w.oaen().set_bit()); PwmTimer { timer, @@ -246,19 +246,19 @@ macro_rules! pwm_timer { fn disable(&mut self, channel: Self::Channel) { match channel { - Channel::CH0 => self.timer.chctl2.modify(|_r, w| w.ch0en().clear_bit()), - Channel::CH1 => self.timer.chctl2.modify(|_r, w| w.ch1en().clear_bit()), - Channel::CH2 => self.timer.chctl2.modify(|_r, w| w.ch2en().clear_bit()), - Channel::CH3 => self.timer.chctl2.modify(|_r, w| w.ch3en().clear_bit()), + Channel::CH0 => self.timer.chctl2().modify(|_r, w| w.ch0en().clear_bit()), + Channel::CH1 => self.timer.chctl2().modify(|_r, w| w.ch1en().clear_bit()), + Channel::CH2 => self.timer.chctl2().modify(|_r, w| w.ch2en().clear_bit()), + Channel::CH3 => self.timer.chctl2().modify(|_r, w| w.ch3en().clear_bit()), } } fn enable(&mut self, channel: Self::Channel) { match channel { - Channel::CH0 => self.timer.chctl2.modify(|_r, w| w.ch0en().set_bit()), - Channel::CH1 => self.timer.chctl2.modify(|_r, w| w.ch1en().set_bit()), - Channel::CH2 => self.timer.chctl2.modify(|_r, w| w.ch2en().set_bit()), - Channel::CH3 => self.timer.chctl2.modify(|_r, w| w.ch3en().set_bit()), + Channel::CH0 => self.timer.chctl2().modify(|_r, w| w.ch0en().set_bit()), + Channel::CH1 => self.timer.chctl2().modify(|_r, w| w.ch1en().set_bit()), + Channel::CH2 => self.timer.chctl2().modify(|_r, w| w.ch2en().set_bit()), + Channel::CH3 => self.timer.chctl2().modify(|_r, w| w.ch3en().set_bit()), } } @@ -281,10 +281,10 @@ macro_rules! pwm_timer { } self.duty[channel as usize] = duty; match channel { - Channel::CH0 => self.timer.ch0cv.write(|w| unsafe { w.bits(duty) }), - Channel::CH1 => self.timer.ch1cv.write(|w| unsafe { w.bits(duty) }), - Channel::CH2 => self.timer.ch2cv.write(|w| unsafe { w.bits(duty) }), - Channel::CH3 => self.timer.ch3cv.write(|w| unsafe { w.bits(duty) }), + Channel::CH0 => self.timer.ch0cv().write(|w| unsafe { w.bits(duty) }), + Channel::CH1 => self.timer.ch1cv().write(|w| unsafe { w.bits(duty) }), + Channel::CH2 => self.timer.ch2cv().write(|w| unsafe { w.bits(duty) }), + Channel::CH3 => self.timer.ch3cv().write(|w| unsafe { w.bits(duty) }), } } @@ -292,8 +292,8 @@ macro_rules! pwm_timer { where P: Into, { - self.timer.ctl0.modify(|_, w| w.cen().clear_bit()); - self.timer.cnt.reset(); + self.timer.ctl0().modify(|_, w| w.cen().clear_bit()); + self.timer.cnt().reset(); let freq = period.into(); @@ -304,8 +304,8 @@ macro_rules! pwm_timer { self.max_duty_cycle = car; self.period = freq; - self.timer.psc.write(|w| unsafe { w.bits(psc) }); - self.timer.car.write(|w| unsafe { w.bits(car) }); + self.timer.psc().write(|w| unsafe { w.bits(psc) }); + self.timer.car().write(|w| unsafe { w.bits(car) }); self.timer.chctl0_output().modify(|_r, w| unsafe { w @@ -329,7 +329,7 @@ macro_rules! pwm_timer { }); // Enable the timer - self.timer.ctl0.write(|w| { + self.timer.ctl0().write(|w| { w .updis().clear_bit() .cen().set_bit() diff --git a/src/rcu.rs b/src/rcu.rs index 5aa694e..96ca951 100644 --- a/src/rcu.rs +++ b/src/rcu.rs @@ -131,49 +131,49 @@ impl UnconfiguredRcu { // Switch to the internal clock let rcu = unsafe { &*crate::pac::RCU::ptr() }; - rcu.ctl.modify(|_, w| w.irc8men().set_bit()); // Enable IRC8M oscillator - while rcu.ctl.read().irc8mstb().bit_is_clear() {} // Wait for oscillator to stabilize - rcu.cfg0.modify(|_, w| unsafe { w.scs().bits(0b00) }); // Switch to the internal oscillator - rcu.ctl.modify(|_, w| w.pllen().clear_bit()); // Disable PLL + rcu.ctl().modify(|_, w| w.irc8men().set_bit()); // Enable IRC8M oscillator + while rcu.ctl().read().irc8mstb().bit_is_clear() {} // Wait for oscillator to stabilize + rcu.cfg0().modify(|_, w| unsafe { w.scs().bits(0b00) }); // Switch to the internal oscillator + rcu.ctl().modify(|_, w| w.pllen().clear_bit()); // Disable PLL // Set bus prescalers - rcu.cfg0.modify(|_, w| unsafe { w.ahbpsc().bits(0b0000) }); // CK_SYS - rcu.cfg0.modify(|_, w| unsafe { w.apb1psc().bits(0b100) }); // CK_AHB / 2 - rcu.cfg0.modify(|_, w| unsafe { w.apb2psc().bits(0b000) }); // CK_AHB + rcu.cfg0().modify(|_, w| unsafe { w.ahbpsc().bits(0b0000) }); // CK_SYS + rcu.cfg0().modify(|_, w| unsafe { w.apb1psc().bits(0b100) }); // CK_AHB / 2 + rcu.cfg0().modify(|_, w| unsafe { w.apb2psc().bits(0b000) }); // CK_AHB let apb1_psc = 2; let apb2_psc = 1; if self.hxtal.is_some() { // Enable external oscillator - rcu.ctl.modify(|_, w| w.hxtalen().set_bit()); + rcu.ctl().modify(|_, w| w.hxtalen().set_bit()); // Wait for oscillator to stabilize - while rcu.ctl.read().hxtalstb().bit_is_clear() {} + while rcu.ctl().read().hxtalstb().bit_is_clear() {} // Select HXTAL as prescaler input source clock - rcu.cfg1.modify(|_, w| w.predv0sel().clear_bit()); + rcu.cfg1().modify(|_, w| w.predv0sel().clear_bit()); // Configure the prescaler - rcu.cfg1.modify(|_, w| unsafe { w.predv0().bits(predv0_bits) }); + rcu.cfg1().modify(|_, w| unsafe { w.predv0().bits(predv0_bits) }); } if use_pll { // Configure PLL input selector - rcu.cfg0.modify(|_, w| w.pllsel().bit(pllsel_bit)); + rcu.cfg0().modify(|_, w| w.pllsel().bit(pllsel_bit)); // Configure PLL multiplier - rcu.cfg0.modify(|_, w| unsafe { w + rcu.cfg0().modify(|_, w| unsafe { w .pllmf_4().bit(pllmf_bits & 0x10 != 0) .pllmf_3_0().bits(pllmf_bits & 0xf) }); // Enable PLL - rcu.ctl.modify(|_, w| w.pllen().set_bit()); + rcu.ctl().modify(|_, w| w.pllen().set_bit()); // Wait for PLL to stabilize - while rcu.ctl.read().pllstb().bit_is_clear() {} + while rcu.ctl().read().pllstb().bit_is_clear() {} } else { // Disable PLL - rcu.ctl.modify(|_, w| w.pllen().clear_bit()); + rcu.ctl().modify(|_, w| w.pllen().clear_bit()); } // Switch to the configured clock source - rcu.cfg0.modify(|_, w| unsafe { w.scs().bits(scs_bits) }); + rcu.cfg0().modify(|_, w| unsafe { w.scs().bits(scs_bits) }); let usbclk_valid; if use_pll { @@ -187,7 +187,7 @@ impl UnconfiguredRcu { usbclk_valid = valid; // Configure USB prescaler - rcu.cfg0.modify(|_, w| unsafe { w.usbfspsc().bits(pr) }); + rcu.cfg0().modify(|_, w| unsafe { w.usbfspsc().bits(pr) }); } else { usbclk_valid = false; } @@ -328,14 +328,14 @@ macro_rules! bus_enable { #[inline(always)] fn enable(rcu: &mut Rcu) { interrupt::free(|_| { - rcu.regs.$apben.modify(|_, w| w.$peren().set_bit()); + rcu.regs.$apben().modify(|_, w| w.$peren().set_bit()); }); } #[inline(always)] fn disable(rcu: &mut Rcu) { interrupt::free(|_| { - rcu.regs.$apben.modify(|_, w| w.$peren().clear_bit()); + rcu.regs.$apben().modify(|_, w| w.$peren().clear_bit()); }); } } @@ -351,8 +351,8 @@ macro_rules! bus { #[inline(always)] fn reset(rcu: &mut Rcu) { interrupt::free(|_| { - rcu.regs.$apbrst.modify(|_, w| w.$perrst().set_bit()); - rcu.regs.$apbrst.modify(|_, w| w.$perrst().clear_bit()); + rcu.regs.$apbrst().modify(|_, w| w.$perrst().set_bit()); + rcu.regs.$apbrst().modify(|_, w| w.$perrst().clear_bit()); }); } } diff --git a/src/rtc.rs b/src/rtc.rs index a2b80da..4bf7893 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -42,8 +42,8 @@ impl Rtc { let prl = LXTAL_HERTZ - 1; assert!(prl < 1 << 20); result.perform_write(|s| { - s.regs.psch.write(|w| unsafe { w.bits(prl >> 16) }); - s.regs.pscl.write(|w| unsafe { w.bits(prl as u16 as u32) }); + s.regs.psch().write(|w| unsafe { w.bits(prl >> 16) }); + s.regs.pscl().write(|w| unsafe { w.bits(prl as u16 as u32) }); }); result @@ -53,7 +53,7 @@ impl Rtc { /// This setting is reset only when the backup domain is reset. fn enable_rtc(_bkp: &mut BackupDomain, _lxtal: &Lxtal) { let rcu = unsafe { &*RCU::ptr() }; - rcu.bdctl.modify(|_, w| { + rcu.bdctl().modify(|_, w| { unsafe { w // Set the source of the RTC to LXTAL @@ -74,9 +74,9 @@ impl Rtc { let prescaler = LXTAL_HERTZ / frequency - 1; self.perform_write(|s| { - s.regs.psch.write(|w| unsafe { w.bits(prescaler >> 16) }); + s.regs.psch().write(|w| unsafe { w.bits(prescaler >> 16) }); s.regs - .pscl + .pscl() .write(|w| unsafe { w.bits(prescaler as u16 as u32) }); }); } @@ -85,10 +85,10 @@ impl Rtc { pub fn set_time(&mut self, counter_value: u32) { self.perform_write(|s| { s.regs - .cnth + .cnth() .write(|w| unsafe { w.bits(counter_value >> 16) }); s.regs - .cntl + .cntl() .write(|w| unsafe { w.bits(counter_value as u16 as u32) }); }); } @@ -105,10 +105,10 @@ impl Rtc { self.perform_write(|s| { s.regs - .alrmh + .alrmh() .write(|w| unsafe { w.alrm().bits((alarm_value >> 16) as u16) }); s.regs - .alrml + .alrml() .write(|w| unsafe { w.alrm().bits(alarm_value as u16) }); }); @@ -119,7 +119,7 @@ impl Rtc { pub fn listen_alarm(&mut self) { // Enable alarm interrupt self.perform_write(|s| { - s.regs.inten.modify(|_, w| w.alrmie().set_bit()); + s.regs.inten().modify(|_, w| w.alrmie().set_bit()); }) } @@ -127,43 +127,43 @@ impl Rtc { pub fn unlisten_alarm(&mut self) { // Disable alarm interrupt self.perform_write(|s| { - s.regs.inten.modify(|_, w| w.alrmie().clear_bit()); + s.regs.inten().modify(|_, w| w.alrmie().clear_bit()); }) } /// Reads the current counter pub fn current_time(&self) -> u32 { // Wait for the APB1 interface to be ready - while !self.regs.ctl.read().rsynf().bit() {} + while !self.regs.ctl().read().rsynf().bit() {} - self.regs.cnth.read().bits() << 16 | self.regs.cntl.read().bits() + self.regs.cnth().read().bits() << 16 | self.regs.cntl.read().bits() } /// Enables the RTC second interrupt. /// This interrupt triggers whenever the RTC counter increases. pub fn listen_seconds(&mut self) { - self.perform_write(|s| s.regs.inten.modify(|_, w| w.scie().set_bit())) + self.perform_write(|s| s.regs.inten().modify(|_, w| w.scie().set_bit())) } /// Disables the RTC second interrupt pub fn unlisten_seconds(&mut self) { - self.perform_write(|s| s.regs.inten.modify(|_, w| w.scie().clear_bit())) + self.perform_write(|s| s.regs.inten().modify(|_, w| w.scie().clear_bit())) } /// Clears the RTC second interrupt flag pub fn clear_second_flag(&mut self) { - self.perform_write(|s| s.regs.ctl.modify(|_, w| w.scif().clear_bit())) + self.perform_write(|s| s.regs.ctl().modify(|_, w| w.scif().clear_bit())) } /// Clears the RTC alarm interrupt flag pub fn clear_alarm_flag(&mut self) { - self.perform_write(|s| s.regs.ctl.modify(|_, w| w.alrmif().clear_bit())) + self.perform_write(|s| s.regs.ctl().modify(|_, w| w.alrmif().clear_bit())) } /// Return `Ok(())` if the second flag is set, `Err(nb::WouldBlock)` otherwise. pub fn wait_second(&mut self) -> nb::Result<(), Infallible> { - if self.regs.ctl.read().scif().bit() { - self.regs.ctl.modify(|_, w| w.scif().clear_bit()); + if self.regs.ctl().read().scif().bit() { + self.regs.ctl().modify(|_, w| w.scif().clear_bit()); Ok(()) } else { Err(nb::Error::WouldBlock) @@ -184,8 +184,8 @@ impl Rtc { ``` */ pub fn wait_alarm(&mut self) -> nb::Result<(), Infallible> { - if self.regs.ctl.read().alrmif().bit() { - self.regs.ctl.modify(|_, w| w.alrmif().clear_bit()); + if self.regs.ctl().read().alrmif().bit() { + self.regs.ctl().modify(|_, w| w.alrmif().clear_bit()); Ok(()) } else { Err(nb::Error::WouldBlock) @@ -199,16 +199,16 @@ impl Rtc { */ fn perform_write(&mut self, func: impl Fn(&mut Self)) { // Wait for the last write operation to be done - while !self.regs.ctl.read().lwoff().bit() {} + while !self.regs.ctl().read().lwoff().bit() {} // Put the clock into config mode - self.regs.ctl.modify(|_, w| w.cmf().set_bit()); + self.regs.ctl().modify(|_, w| w.cmf().set_bit()); // Perform the write operation func(self); // Take the device out of config mode - self.regs.ctl.modify(|_, w| w.cmf().clear_bit()); + self.regs.ctl().modify(|_, w| w.cmf().clear_bit()); // Wait for the write to be done - while !self.regs.ctl.read().lwoff().bit() {} + while !self.regs.ctl().read().lwoff().bit() {} } } diff --git a/src/serial.rs b/src/serial.rs index a28918a..12d41a3 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -267,12 +267,12 @@ impl Serial USART::remap(afio, PINS::REMAP); // enable DMA transfers - usart.ctl2.write(|w| w.dent().set_bit().denr().set_bit()); + usart.ctl2().write(|w| w.dent().set_bit().denr().set_bit()); // Configure baud rate let brr = USART::base_frequency(rcu).0 / config.baudrate.0; assert!(brr >= 16, "impossible baud rate"); - usart.baud.write(|w| unsafe { w.bits(brr) }); + usart.baud().write(|w| unsafe { w.bits(brr) }); // Configure parity and word length // Unlike most uart devices, the "word length" of this usart device refers to @@ -284,7 +284,7 @@ impl Serial Parity::ParityEven => (true, true, false), Parity::ParityOdd => (true, true, true), }; - usart.ctl0.modify(|_r, w| { + usart.ctl0().modify(|_r, w| { w.wl().bit(word_length); w.pm().bit(parity); w.pcen().bit(parity_control_enable) @@ -297,14 +297,14 @@ impl Serial StopBits::STOP2 => 0b10, StopBits::STOP1P5 => 0b11, }; - usart.ctl1.modify(|_r, w| unsafe { + usart.ctl1().modify(|_r, w| unsafe { w.stb().bits(stop_bits) }); // UE: enable USART // RE: enable receiver // TE: enable transceiver - usart.ctl0.modify(|_r, w| { + usart.ctl0().modify(|_r, w| { w.uen().set_bit(); w.ren().set_bit(); w.ten().set_bit() @@ -318,8 +318,8 @@ impl Serial /// register empty (TXE)_ interrupt pub fn listen(&mut self, event: Event) { match event { - Event::Rxne => self.usart.ctl0.modify(|_, w| w.rbneie().set_bit()), - Event::Txe => self.usart.ctl0.modify(|_, w| w.tbeie().set_bit()), + Event::Rxne => self.usart.ctl0().modify(|_, w| w.rbneie().set_bit()), + Event::Txe => self.usart.ctl0().modify(|_, w| w.tbeie().set_bit()), } } @@ -328,8 +328,8 @@ impl Serial /// register empty (TXE)_ interrupt pub fn unlisten(&mut self, event: Event) { match event { - Event::Rxne => self.usart.ctl0.modify(|_, w| w.rbneie().clear_bit()), - Event::Txe => self.usart.ctl0.modify(|_, w| w.tbeie().clear_bit()), + Event::Rxne => self.usart.ctl0().modify(|_, w| w.rbneie().clear_bit()), + Event::Txe => self.usart.ctl0().modify(|_, w| w.tbeie().clear_bit()), } } @@ -354,21 +354,21 @@ impl Serial impl Tx { pub fn listen(&mut self) { - unsafe { (*USART::ptr()).ctl0.modify(|_, w| w.tbeie().set_bit()) }; + unsafe { (*USART::ptr()).ctl0().modify(|_, w| w.tbeie().set_bit()) }; } pub fn unlisten(&mut self) { - unsafe { (*USART::ptr()).ctl0.modify(|_, w| w.tbeie().clear_bit()) }; + unsafe { (*USART::ptr()).ctl0().modify(|_, w| w.tbeie().clear_bit()) }; } } impl Rx { pub fn listen(&mut self) { - unsafe { (*USART::ptr()).ctl0.modify(|_, w| w.rbneie().set_bit()) }; + unsafe { (*USART::ptr()).ctl0().modify(|_, w| w.rbneie().set_bit()) }; } pub fn unlisten(&mut self) { - unsafe { (*USART::ptr()).ctl0.modify(|_, w| w.rbneie().clear_bit()) }; + unsafe { (*USART::ptr()).ctl0().modify(|_, w| w.rbneie().clear_bit()) }; } } @@ -377,7 +377,7 @@ impl crate::hal::serial::Read for Rx { fn read(&mut self) -> nb::Result { // NOTE(unsafe) atomic read with no side effects - let sr = unsafe { (*USART::ptr()).stat.read() }; + let sr = unsafe { (*USART::ptr()).stat().read() }; // Check for any errors let err = if sr.perr().bit_is_set() { @@ -398,8 +398,8 @@ impl crate::hal::serial::Read for Rx { // register // NOTE(read_volatile) see `write_volatile` below unsafe { - ptr::read_volatile(&(*USART::ptr()).stat as *const _ as *const _); - ptr::read_volatile(&(*USART::ptr()).data as *const _ as *const _); + ptr::read_volatile(&(*USART::ptr()).stat() as *const _ as *const _); + ptr::read_volatile(&(*USART::ptr()).data() as *const _ as *const _); } Err(nb::Error::Other(err)) } else { @@ -408,7 +408,7 @@ impl crate::hal::serial::Read for Rx { // Read the received byte // NOTE(read_volatile) see `write_volatile` below Ok(unsafe { - ptr::read_volatile(&(*USART::ptr()).data as *const _ as *const _) + ptr::read_volatile(&(*USART::ptr()).data() as *const _ as *const _) }) } else { Err(nb::Error::WouldBlock) @@ -422,14 +422,14 @@ impl crate::hal::serial::Write for Tx { fn write(&mut self, byte: u8) -> nb::Result<(), Self::Error> { // NOTE(unsafe) atomic read with no side effects - let sr = unsafe { (*USART::ptr()).stat.read() }; + let sr = unsafe { (*USART::ptr()).stat().read() }; if sr.tbe().bit_is_set() { // NOTE(unsafe) atomic write to stateless register // NOTE(write_volatile) 8-bit write that's not possible through the svd2rust API unsafe { let usart_mut = USART::ptr() as *mut USART::Target; - ptr::write_volatile(ptr::addr_of_mut!((*usart_mut).data) as *mut u8, byte); + ptr::write_volatile(ptr::addr_of_mut!((*usart_mut).data()) as *mut u8, byte); } Ok(()) } else { @@ -439,7 +439,7 @@ impl crate::hal::serial::Write for Tx { fn flush(&mut self) -> nb::Result<(), Self::Error> { // NOTE(unsafe) atomic read with no side effects - let sr = unsafe { (*USART::ptr()).stat.read() }; + let sr = unsafe { (*USART::ptr()).stat().read() }; if sr.tc().bit_is_set() { Ok(()) diff --git a/src/spi.rs b/src/spi.rs index dc1c68b..deddb01 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -111,7 +111,7 @@ impl Spi where SPI: SpiX SPI::reset(rcu); // disable SS output - spi.ctl1.write(|w| w.nssdrv().clear_bit()); + spi.ctl1().write(|w| w.nssdrv().clear_bit()); let base_freq = SPI::base_frequency(rcu); @@ -131,7 +131,7 @@ impl Spi where SPI: SpiX // lsbfirst: MSB first // ssm: enable software slave management (NSS pin free for other uses) // ssi: set nss high = master mode - spi.ctl0.write(|w| unsafe { w + spi.ctl0().write(|w| unsafe { w .ckph().bit(mode.phase == Phase::CaptureOnSecondTransition) .ckpl().bit(mode.polarity == Polarity::IdleHigh) .mstmod().set_bit() // Master mode @@ -166,10 +166,10 @@ impl Spi where SPI: SpiX }; // Disable SPI - self.spi.ctl0.modify(|_, w| { w.spien().clear_bit()}); + self.spi.ctl0().modify(|_, w| { w.spien().clear_bit()}); // Restore config, change frequency and re-enable SPI - self.spi.ctl0.modify( |_, w| unsafe { w + self.spi.ctl0().modify( |_, w| unsafe { w .psc().bits(br) .spien().set_bit() }); @@ -184,7 +184,7 @@ impl crate::hal::spi::FullDuplex for Spi { type Error = Error; fn read(&mut self) -> nb::Result { - let sr = self.spi.stat.read(); + let sr = self.spi.stat().read(); Err(if sr.rxorerr().bit_is_set() { nb::Error::Other(Error::Overrun) @@ -193,7 +193,7 @@ impl crate::hal::spi::FullDuplex for Spi { } else if sr.crcerr().bit_is_set() { nb::Error::Other(Error::Crc) } else if sr.rbne().bit_is_set() { - let byte = (self.spi.data.read().bits() & 0xff) as u8; + let byte = (self.spi.data().read().bits() & 0xff) as u8; return Ok(byte); } else { nb::Error::WouldBlock @@ -201,7 +201,7 @@ impl crate::hal::spi::FullDuplex for Spi { } fn send(&mut self, byte: u8) -> nb::Result<(), Error> { - let sr = self.spi.stat.read(); + let sr = self.spi.stat().read(); Err(if sr.rxorerr().bit_is_set() { nb::Error::Other(Error::Overrun) @@ -210,7 +210,7 @@ impl crate::hal::spi::FullDuplex for Spi { } else if sr.crcerr().bit_is_set() { nb::Error::Other(Error::Crc) } else if sr.tbe().bit_is_set() { - self.spi.data.write(|w| unsafe { w.bits(byte as u16) }); + self.spi.data().write(|w| unsafe { w.bits(byte as u16) }); return Ok(()); } else { nb::Error::WouldBlock diff --git a/src/timer.rs b/src/timer.rs index 70d78b2..c1c3bdb 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -41,25 +41,25 @@ macro_rules! hal { /// Starts listening for an `event` pub fn listen(&mut self, event: Event) { match event { - Event::Update => self.tim.dmainten.modify(|_, w| w.upie().set_bit()), + Event::Update => self.tim.dmainten().modify(|_, w| w.upie().set_bit()), } } /// Stops listening for an `event` pub fn unlisten(&mut self, event: Event) { match event { - Event::Update => self.tim.dmainten.modify(|_, w| w.upie().clear_bit()), + Event::Update => self.tim.dmainten().modify(|_, w| w.upie().clear_bit()), } } /// Clears Update Interrupt Flag pub fn clear_update_interrupt_flag(&mut self) { - self.tim.intf.modify(|_, w| w.upif().clear_bit()); + self.tim.intf().modify(|_, w| w.upif().clear_bit()); } /// Releases the TIMER peripheral pub fn free(self) -> $TIM { - self.tim.ctl0.modify(|_, w| w.cen().clear_bit()); + self.tim.ctl0().modify(|_, w| w.cen().clear_bit()); self.tim } } @@ -75,35 +75,35 @@ macro_rules! hal { { self.timeout = timeout.into(); - self.tim.ctl0.modify(|_, w| w.cen().clear_bit()); - self.tim.cnt.reset(); + self.tim.ctl0().modify(|_, w| w.cen().clear_bit()); + self.tim.cnt().reset(); let ticks = self.timer_clock.0 / self.timeout.0; let psc = ((ticks - 1) / (1 << 16)) as u16; let car = (ticks / ((psc + 1) as u32)) as u16; - self.tim.psc.write(|w| unsafe { w.bits(psc) } ); - self.tim.car.write(|w| unsafe { w.bits(car) } ); + self.tim.psc().write(|w| unsafe { w.bits(psc) } ); + self.tim.car().write(|w| unsafe { w.bits(car) } ); // Set UPS=1 so an UPG will *not* trigger an interrupt - self.tim.ctl0.modify(|_, w| w.ups().set_bit()); + self.tim.ctl0().modify(|_, w| w.ups().set_bit()); // Trigger an UPG to clear the timer counter register // see user manual (v1.2) p.261 for details - self.tim.swevg.write(|w| w.upg().set_bit()); + self.tim.swevg().write(|w| w.upg().set_bit()); // clear any outstanding UPIF flag to ensure a clear start - self.tim.intf.modify(|_, w| w.upif().clear_bit()); + self.tim.intf().modify(|_, w| w.upif().clear_bit()); - self.tim.ctl0.write(|w| { w + self.tim.ctl0().write(|w| { w .updis().clear_bit() .cen().set_bit() }); } fn wait(&mut self) -> nb::Result<(), Void> { - if self.tim.intf.read().upif().bit_is_clear() { + if self.tim.intf().read().upif().bit_is_clear() { Err(nb::Error::WouldBlock) } else { - self.tim.intf.modify(|_r, w| w.upif().clear_bit()); + self.tim.intf().modify(|_r, w| w.upif().clear_bit()); Ok(()) } } diff --git a/src/watchdog.rs b/src/watchdog.rs index 79bfd8f..2d09a4d 100644 --- a/src/watchdog.rs +++ b/src/watchdog.rs @@ -28,7 +28,7 @@ impl FreeWatchdog { /// Free watchdog stopped when core is halted pub fn stop_on_debug(&self, dbg: &DBG, stop: bool) { - dbg.ctl.modify(|_, w| w.fwdgt_hold().bit(stop)); + dbg.ctl().modify(|_, w| w.fwdgt_hold().bit(stop)); } fn setup(&self, timeout_ms: u32) { @@ -42,21 +42,21 @@ impl FreeWatchdog { let rl = (timeout_ms * max_rl / max_period).min(max_rl) as u16; self.access_registers(|fwdgt| { - fwdgt.psc.modify(|_, w| unsafe { w.psc().bits(pr) }); - fwdgt.rld.modify(|_, w| unsafe { w.rld().bits(rl) }); + fwdgt.psc().modify(|_, w| unsafe { w.psc().bits(pr) }); + fwdgt.rld().modify(|_, w| unsafe { w.rld().bits(rl) }); }); } fn is_pr_updating(&self) -> bool { - self.fwdgt.stat.read().pud().bit() + self.fwdgt.stat().read().pud().bit() } /// Returns the interval in ms pub fn interval(&self) -> MilliSeconds { while self.is_pr_updating() {} - let pr = self.fwdgt.psc.read().psc().bits(); - let rl = self.fwdgt.rld.read().rld().bits(); + let pr = self.fwdgt.psc().read().psc().bits(); + let rl = self.fwdgt.rld().read().rld().bits(); let ms = Self::timeout_period(pr, rl); MilliSeconds(ms) @@ -83,13 +83,13 @@ impl FreeWatchdog { fn access_registers A>(&self, mut f: F) -> A { // Unprotect write access to registers self.fwdgt - .ctl + .ctl() .write(|w| unsafe { w.cmd().bits(CMD_ACCESS) }); let a = f(&self.fwdgt); // Protect again self.fwdgt - .ctl + .ctl() .write(|w| unsafe { w.cmd().bits(CMD_RELOAD) }); a } @@ -101,14 +101,14 @@ impl WatchdogEnable for FreeWatchdog { fn start>(&mut self, period: T) { self.setup(period.into().0); - self.fwdgt.ctl.write(|w| unsafe { w.cmd().bits(CMD_START) }); + self.fwdgt.ctl().write(|w| unsafe { w.cmd().bits(CMD_START) }); } } impl Watchdog for FreeWatchdog { fn feed(&mut self) { self.fwdgt - .ctl + .ctl() .write(|w| unsafe { w.cmd().bits(CMD_RELOAD) }); } } From 12bd85972fe377ff826b82574816d9829bbbad2e Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 14:37:12 +0200 Subject: [PATCH 4/7] Fix address of mut --- src/dma.rs | 2 +- src/serial.rs | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/dma.rs b/src/dma.rs index 9037a3c..6febb72 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -235,7 +235,7 @@ macro_rules! dma { } pub fn intc(&self) -> &$dmaX::INTC { - unsafe { &(*$DMAX::ptr()).intc } + unsafe { &(*$DMAX::ptr()).intc() } } pub fn ctl(&self) -> &$dmaX::$CTLX { diff --git a/src/serial.rs b/src/serial.rs index 12d41a3..94c0846 100644 --- a/src/serial.rs +++ b/src/serial.rs @@ -429,7 +429,8 @@ impl crate::hal::serial::Write for Tx { // NOTE(write_volatile) 8-bit write that's not possible through the svd2rust API unsafe { let usart_mut = USART::ptr() as *mut USART::Target; - ptr::write_volatile(ptr::addr_of_mut!((*usart_mut).data()) as *mut u8, byte); + let mut v = (*usart_mut).data(); + ptr::write_volatile(ptr::addr_of_mut!(v) as *mut u8, byte); } Ok(()) } else { From ae86bb34a6054a24833561b6edd7294f9a1788f5 Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 14:41:36 +0200 Subject: [PATCH 5/7] clicints --- src/eclic.rs | 36 ++++++++++++++++++------------------ src/rtc.rs | 2 +- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/eclic.rs b/src/eclic.rs index e4a73be..baaaa81 100644 --- a/src/eclic.rs +++ b/src/eclic.rs @@ -130,12 +130,12 @@ impl EclicExt for ECLIC { eclic.mth().write(|w| unsafe { w.bits(0) }); for nr in 0..eclic.clicinfo().read().num_interrupt().bits() as usize { - eclic.clicints[nr].clicintip.write(|w| unsafe { w.bits(0) }); - eclic.clicints[nr].clicintie.write(|w| unsafe { w.bits(0) }); - eclic.clicints[nr] + eclic.clicints(nr).clicintip.write(|w| unsafe { w.bits(0) }); + eclic.clicints(nr).clicintie.write(|w| unsafe { w.bits(0) }); + eclic.clicints(nr) .clicintattr .write(|w| unsafe { w.bits(0) }); - eclic.clicints[nr] + eclic.clicints(nr) .clicintctl .write(|w| unsafe { w.bits(0) }); } @@ -190,7 +190,7 @@ impl EclicExt for ECLIC { #[inline] unsafe fn unmask(interrupt: Interrupt) { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintie .write(|w| w.ie().set_bit()) } @@ -198,7 +198,7 @@ impl EclicExt for ECLIC { #[inline] fn mask(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintie .write(|w| w.ie().clear_bit()) } @@ -207,7 +207,7 @@ impl EclicExt for ECLIC { #[inline] fn is_enabled(interrupt: Interrupt) -> bool { unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintie .read() .ie() @@ -218,7 +218,7 @@ impl EclicExt for ECLIC { #[inline] fn pend(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintip .write(|w| w.ip().set_bit()) } @@ -227,7 +227,7 @@ impl EclicExt for ECLIC { #[inline] fn unpend(interrupt: Interrupt) { unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintip .write(|w| w.ip().clear_bit()) } @@ -236,7 +236,7 @@ impl EclicExt for ECLIC { #[inline] fn is_pending(interrupt: Interrupt) -> bool { unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintip .read() .ip() @@ -247,7 +247,7 @@ impl EclicExt for ECLIC { #[inline] fn set_trigger_type(interrupt: Interrupt, tt: TriggerType) { unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintattr .write(|w| w.trig().bits(tt as u8).shv().clear_bit()) } @@ -255,7 +255,7 @@ impl EclicExt for ECLIC { #[inline] fn get_trigger_type(interrupt: Interrupt) -> Option { - match unsafe { (*Self::ptr()).clicints[interrupt as usize].clicintattr.read().trig().bits() } { + match unsafe { (*Self::ptr()).clicints(interrupt as usize).clicintattr.read().trig().bits() } { 0 => Some(TriggerType::Level), 1 => Some(TriggerType::RisingEdge), 3 => Some(TriggerType::FallingEdge), @@ -266,7 +266,7 @@ impl EclicExt for ECLIC { #[inline] fn set_level(interrupt: Interrupt, level: Level) { let mut intctl = unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintctl .read() .level_priority() @@ -281,7 +281,7 @@ impl EclicExt for ECLIC { let level = level << (8 - level_bits); unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintctl .write(|w| w.level_priority().bits(intctl | level)) } @@ -290,7 +290,7 @@ impl EclicExt for ECLIC { #[inline] fn get_level(interrupt: Interrupt) -> Level { let intctl = unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintctl .read() .level_priority() @@ -306,7 +306,7 @@ impl EclicExt for ECLIC { #[inline] fn set_priority(interrupt: Interrupt, priority: Priority) { let mut intctl = unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintctl .read() .level_priority() @@ -324,7 +324,7 @@ impl EclicExt for ECLIC { let priority = priority << (8 - EFFECTIVE_LEVEL_PRIORITY_BITS); unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintctl .write(|w| w.level_priority().bits(intctl | priority)) } @@ -333,7 +333,7 @@ impl EclicExt for ECLIC { #[inline] fn get_priority(interrupt: Interrupt) -> Priority { let intctl = unsafe { - (*Self::ptr()).clicints[interrupt as usize] + (*Self::ptr()).clicints(interrupt as usize) .clicintctl .read() .level_priority() diff --git a/src/rtc.rs b/src/rtc.rs index 4bf7893..0ee0a59 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -136,7 +136,7 @@ impl Rtc { // Wait for the APB1 interface to be ready while !self.regs.ctl().read().rsynf().bit() {} - self.regs.cnth().read().bits() << 16 | self.regs.cntl.read().bits() + self.regs.cnth().read().bits() << 16 | self.regs.cntl().read().bits() } /// Enables the RTC second interrupt. From 77c50d65852ce559df5471534bcc0e38cfe77be7 Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 14:42:19 +0200 Subject: [PATCH 6/7] regs --- src/eclic.rs | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/eclic.rs b/src/eclic.rs index baaaa81..8f25c63 100644 --- a/src/eclic.rs +++ b/src/eclic.rs @@ -130,13 +130,13 @@ impl EclicExt for ECLIC { eclic.mth().write(|w| unsafe { w.bits(0) }); for nr in 0..eclic.clicinfo().read().num_interrupt().bits() as usize { - eclic.clicints(nr).clicintip.write(|w| unsafe { w.bits(0) }); - eclic.clicints(nr).clicintie.write(|w| unsafe { w.bits(0) }); + eclic.clicints(nr).clicintip().write(|w| unsafe { w.bits(0) }); + eclic.clicints(nr).clicintie().write(|w| unsafe { w.bits(0) }); eclic.clicints(nr) - .clicintattr + .clicintattr() .write(|w| unsafe { w.bits(0) }); eclic.clicints(nr) - .clicintctl + .clicintctl() .write(|w| unsafe { w.bits(0) }); } } @@ -191,7 +191,7 @@ impl EclicExt for ECLIC { #[inline] unsafe fn unmask(interrupt: Interrupt) { (*Self::ptr()).clicints(interrupt as usize) - .clicintie + .clicintie() .write(|w| w.ie().set_bit()) } @@ -199,7 +199,7 @@ impl EclicExt for ECLIC { fn mask(interrupt: Interrupt) { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintie + .clicintie() .write(|w| w.ie().clear_bit()) } } @@ -208,7 +208,7 @@ impl EclicExt for ECLIC { fn is_enabled(interrupt: Interrupt) -> bool { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintie + .clicintie() .read() .ie() .bit_is_set() @@ -219,7 +219,7 @@ impl EclicExt for ECLIC { fn pend(interrupt: Interrupt) { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintip + .clicintip() .write(|w| w.ip().set_bit()) } } @@ -228,7 +228,7 @@ impl EclicExt for ECLIC { fn unpend(interrupt: Interrupt) { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintip + .clicintip() .write(|w| w.ip().clear_bit()) } } @@ -237,7 +237,7 @@ impl EclicExt for ECLIC { fn is_pending(interrupt: Interrupt) -> bool { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintip + .clicintip() .read() .ip() .bit_is_set() @@ -248,14 +248,14 @@ impl EclicExt for ECLIC { fn set_trigger_type(interrupt: Interrupt, tt: TriggerType) { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintattr + .clicintattr() .write(|w| w.trig().bits(tt as u8).shv().clear_bit()) } } #[inline] fn get_trigger_type(interrupt: Interrupt) -> Option { - match unsafe { (*Self::ptr()).clicints(interrupt as usize).clicintattr.read().trig().bits() } { + match unsafe { (*Self::ptr()).clicints(interrupt as usize).clicintattr().read().trig().bits() } { 0 => Some(TriggerType::Level), 1 => Some(TriggerType::RisingEdge), 3 => Some(TriggerType::FallingEdge), @@ -267,7 +267,7 @@ impl EclicExt for ECLIC { fn set_level(interrupt: Interrupt, level: Level) { let mut intctl = unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintctl + .clicintctl() .read() .level_priority() .bits() @@ -282,7 +282,7 @@ impl EclicExt for ECLIC { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintctl + .clicintctl() .write(|w| w.level_priority().bits(intctl | level)) } } @@ -291,7 +291,7 @@ impl EclicExt for ECLIC { fn get_level(interrupt: Interrupt) -> Level { let intctl = unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintctl + .clicintctl() .read() .level_priority() .bits() @@ -307,7 +307,7 @@ impl EclicExt for ECLIC { fn set_priority(interrupt: Interrupt, priority: Priority) { let mut intctl = unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintctl + .clicintctl() .read() .level_priority() .bits() @@ -325,7 +325,7 @@ impl EclicExt for ECLIC { unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintctl + .clicintctl() .write(|w| w.level_priority().bits(intctl | priority)) } } @@ -334,7 +334,7 @@ impl EclicExt for ECLIC { fn get_priority(interrupt: Interrupt) -> Priority { let intctl = unsafe { (*Self::ptr()).clicints(interrupt as usize) - .clicintctl + .clicintctl() .read() .level_priority() .bits() From 023a60ade716c955ab8f71467d999dc4586ee935 Mon Sep 17 00:00:00 2001 From: dcz Date: Fri, 26 Sep 2025 14:46:10 +0200 Subject: [PATCH 7/7] regs in dma --- src/dma.rs | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/dma.rs b/src/dma.rs index 6febb72..4040a42 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -231,27 +231,27 @@ macro_rules! dma { pub fn intf(&self) -> $dmaX::intf::R { // NOTE(unsafe) atomic read with no side effects - unsafe { (*$DMAX::ptr()).intf().read() } + unsafe { &*$DMAX::ptr() }.intf().read() } pub fn intc(&self) -> &$dmaX::INTC { - unsafe { &(*$DMAX::ptr()).intc() } + unsafe { &*$DMAX::ptr() }.intc() } pub fn ctl(&self) -> &$dmaX::$CTLX { - unsafe { &(*$DMAX::ptr()).$ctlX } + unsafe { &*$DMAX::ptr() }.$ctlX() } pub fn cnt(&self) -> &$dmaX::$CNTX { - unsafe { &(*$DMAX::ptr()).$cntX } + unsafe { &*$DMAX::ptr() }.$cntX() } pub fn paddr(&self) -> &$dmaX::$PADDRX { - unsafe { &(*$DMAX::ptr()).$paddrX } + unsafe { &*$DMAX::ptr() }.$paddrX() } pub fn maddr(&self) -> &$dmaX::$MADDRX { - unsafe { &(*$DMAX::ptr()).$maddrX } + unsafe { &*$DMAX::ptr() }.$maddrX() } }