Uncached address; DMAC design

Author: luojia65

Cargo.toml

@@ -3,7 +3,7 @@ name = "k210-hal"
 version = "0.2.0"
 authors = ["The RISC-V Team <[email protected]>"]
 categories = ["embedded", "hardware-support", "no-std"]
-description = "HAL for K210 SoC"
+description = "Hardware Abstract Layer (HAL) support for K210, dual-core RV64GC SoC"
 repository = "https://github.com/riscv-rust/k210-hal"
 keywords = ["riscv", "k210", "hal"]
 license = "ISC"

src/cache.rs

@@ -0,0 +1,81 @@
+//! (TODO) Bypass cache 
+//! 
+//! Todo: verify this module!
+
+use core::slice;
+
+/// Convert a buffer or a pointer into ones with uncached address.
+/// 
+/// Section 3.4.1, Kendryte K210 Datasheet
+pub fn uncached<T: Uncache>(buf: T) -> T {
+    buf.uncache()
+}
+
+/// Uncacheable buffer or pointer.
+pub trait Uncache {
+    /// Convert this buffer or pointer to uncached addressed ones
+    fn uncache(self) -> Self;
+}
+
+impl<T> Uncache for &T {
+    #[inline]
+    fn uncache(self) -> Self {
+        let addr = self as *const T as usize;
+        assert_addr_cached(addr);
+        // note(unsafe): safe for source address is safe
+        unsafe { &*((addr - 0x4000_0000) as *const T) }
+    }
+}
+
+impl<T> Uncache for &mut T {
+    #[inline]
+    fn uncache(self) -> Self {
+        let addr = self as *mut T as usize;
+        assert_addr_cached(addr);
+        // note(unsafe): safe for source address is safe
+        unsafe { &mut *((addr - 0x4000_0000) as *mut T) }
+    }
+}
+
+impl<T> Uncache for &[T] {
+    #[inline]
+    fn uncache(self) -> Self {
+        let addr = self.as_ptr() as usize;
+        assert_addr_cached(addr);
+        let new_ptr = (addr - 0x4000_0000) as *const T;
+        // note(unsafe): source address is safe; passing ownership
+        unsafe { slice::from_raw_parts(new_ptr, self.len()) }
+    }
+}
+
+impl<T> Uncache for &mut [T] {
+    #[inline]
+    fn uncache(self) -> Self {
+        let addr = self.as_ptr() as usize;
+        assert_addr_cached(addr);
+        let new_ptr = (addr - 0x4000_0000) as *mut T;
+        // note(unsafe): source address is safe; passing ownership
+        unsafe { slice::from_raw_parts_mut(new_ptr, self.len()) }
+    }
+}
+
+impl<T> Uncache for *const T {
+    #[inline]
+    fn uncache(self) -> Self {
+        assert_addr_cached(self as usize);
+        (self as usize - 0x4000_0000) as *const T
+    }
+}
+
+impl<T> Uncache for *mut T {
+    #[inline]
+    fn uncache(self) -> Self {
+        assert_addr_cached(self as usize);
+        (self as usize - 0x4000_0000) as *mut T
+    }
+}
+
+#[inline]
+fn assert_addr_cached(addr: usize) {
+    assert!(addr <= 0x805F_FFFF && addr >= 0x8000_0000);
+}

src/dmac.rs

@@ -1 +1,34 @@
 //! (TODO) Direct Memory Access Controller (DMAC)
+use crate::{pac, sysctl};
+
+pub fn dmac_id() -> u64 {
+    unsafe { (*pac::DMAC::ptr()).id.read().bits() }
+}
+
+pub fn dmac_version() -> u64 {
+    unsafe { (*pac::DMAC::ptr()).compver.read().bits() }
+}
+
+pub trait DmacExt {
+    fn configure(self, /* sysctl ACLK clock */) -> Dmac;
+}
+
+impl DmacExt for pac::DMAC {
+    fn configure(self, /* sysctl ACLK clock */) -> Dmac {
+        // enable
+        sysctl::clk_en_peri().modify(|_, w| w.dma_clk_en().set_bit());
+        // todo: reset
+        Dmac {} // todo
+    }
+}
+
+pub struct Dmac {
+
+}
+
+// pub struct C0 {
+//     // todo
+//     pub async fn poll() {
+        
+//     }
+// }

src/lib.rs

@@ -9,6 +9,7 @@ pub use k210_pac as pac;
 
 pub mod aes;
 pub mod apu;
+pub mod cache;
 pub mod clint;
 pub mod clock;
 pub mod dmac;