Bump riscv to v0.10.1

Since Longan Nano GD32VF103 chip only supports
a single hart, still safe to use the recently-
updated riscv crate interrupt free section
which only disables interrupts for the current hart.

Author: a-gavin

Cargo.toml

@@ -18,7 +18,7 @@ default-target = "x86_64-unknown-linux-gnu"
 gd32vf103xx-hal = "0.5.0"
 embedded-hal = "0.2.6"
 nb = "1.0.0"
-riscv = "0.6.0"
+riscv = "0.10.1"
 st7735-lcd = { version = "0.8.1", optional = true }
 embedded-sdmmc = { version = "0.3.0", optional = true }
 

src/stdout.rs

@@ -57,7 +57,7 @@ pub fn configure<X, Y>(
     let serial = Serial::new(uart, (tx, rx), config, afio, rcu);
     let (tx, _) = serial.split();
 
-    interrupt::free(|_| {
+    interrupt::free(|| {
         unsafe {
             STDOUT.replace(SerialWrapper(tx));
         }
@@ -66,7 +66,7 @@ pub fn configure<X, Y>(
 
 /// Writes string to stdout
 pub fn write_str(s: &str) {
-    interrupt::free(|_| unsafe {
+    interrupt::free(|| unsafe {
         if let Some(stdout) = STDOUT.as_mut() {
             let _ = stdout.write_str(s);
         }
@@ -75,7 +75,7 @@ pub fn write_str(s: &str) {
 
 /// Writes formatted string to stdout
 pub fn write_fmt(args: fmt::Arguments) {
-    interrupt::free(|_| unsafe {
+    interrupt::free(|| unsafe {
         if let Some(stdout) = STDOUT.as_mut() {
             let _ = stdout.write_fmt(args);
         }