Skip to content

Commit 66ab965

Browse files
icebergfuavpatel
icebergfu
authored and
avpatel
committed
platform: generic: mips: add P8700
Extend generic platform to support MIPS P8700. Signed-off-by: Chao-ying Fu <[email protected]> Reviewed-by: Anup Patel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Anup Patel <[email protected]>
1 parent 3f8159a commit 66ab965

File tree

7 files changed

+517
-0
lines changed

7 files changed

+517
-0
lines changed

‎platform/generic/Kconfig‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,10 @@ config PLATFORM_THEAD
6868
select THEAD_C9XX_PMU
6969
default n
7070

71+
config PLATFORM_MIPS_P8700
72+
bool "MIPS P8700 support"
73+
default n
74+
7175
source "$(OPENSBI_SRC_DIR)/platform/generic/andes/Kconfig"
7276
source "$(OPENSBI_SRC_DIR)/platform/generic/thead/Kconfig"
7377

‎platform/generic/configs/defconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ CONFIG_PLATFORM_SIFIVE_FU740=y
66
CONFIG_PLATFORM_SOPHGO_SG2042=y
77
CONFIG_PLATFORM_STARFIVE_JH7110=y
88
CONFIG_PLATFORM_THEAD=y
9+
CONFIG_PLATFORM_MIPS_P8700=y
910
CONFIG_FDT_CPPC=y
1011
CONFIG_FDT_CPPC_RPMI=y
1112
CONFIG_FDT_GPIO=y

‎platform/generic/include/mips/board.h‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
/*
2+
* SPDX-License-Identifier: BSD-2-Clause
3+
*
4+
* Copyright (c) 2025 MIPS
5+
*
6+
*/
7+
8+
#ifndef __BOARD_H__
9+
#define __BOARD_H__
10+
11+
/* Please review all defines to change for your board. */
12+
13+
/* Use in stw.S, p8700.c, p8700.h, mips-cm.h */
14+
#define CM_BASE 0x16100000
15+
16+
/* Use in mips-cm.h, p8700.c */
17+
#define CLUSTERS_IN_PLATFORM 1
18+
#if CLUSTERS_IN_PLATFORM > 1
19+
/* Define global CM bases for cluster 0, 1, 2, and more. */
20+
#define GLOBAL_CM_BASE0 0
21+
#define GLOBAL_CM_BASE1 0
22+
#define GLOBAL_CM_BASE2 0
23+
#endif
24+
25+
/* Use in stw.S */
26+
#define TIMER_ADDR (CM_BASE + 0x8050)
27+
28+
/* Use in cps-vec.S */
29+
#define DRAM_ADDRESS 0x80000000
30+
#define DRAM_SIZE 0x80000000
31+
#define DRAM_PMP_ADDR ((DRAM_ADDRESS >> 2) | ((DRAM_SIZE - 1) >> 3))
32+
33+
#endif

‎platform/generic/include/mips/mips-cm.h‎

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
1+
/*
2+
* SPDX-License-Identifier: BSD-2-Clause
3+
*
4+
* Copyright (c) 2025 MIPS
5+
*
6+
*/
7+
8+
#ifndef __MIPS_CM_H__
9+
#define __MIPS_CM_H__
10+
11+
#include <mips/p8700.h>
12+
#include <sbi/sbi_console.h>
13+
14+
/* Define 1 to print out CM read and write info */
15+
#define DEBUG_CM 0
16+
17+
#if CLUSTERS_IN_PLATFORM > 1
18+
static long GLOBAL_CM_BASE[CLUSTERS_IN_PLATFORM] = {GLOBAL_CM_BASE0, GLOBAL_CM_BASE1, GLOBAL_CM_BASE2};
19+
#else
20+
static long GLOBAL_CM_BASE[CLUSTERS_IN_PLATFORM] = {CM_BASE};
21+
#endif
22+
23+
#define CPS_ACCESSOR_R(unit, sz, base, off, name) \
24+
static inline u##sz read_##unit##_##name(u32 hartid, bool local_p) \
25+
{ \
26+
u##sz value; \
27+
long cmd_reg; \
28+
int cl, co; \
29+
cl = cpu_cluster(hartid); \
30+
co = cpu_core(hartid); \
31+
cmd_reg = (local_p ? (base) : ((base) - CM_BASE + GLOBAL_CM_BASE[cl])) \
32+
+ (co << CM_BASE_CORE_SHIFT) \
33+
+ off; \
34+
if (DEBUG_CM) \
35+
sbi_printf("CM READ%d cmd_reg=%lx\n", sz, cmd_reg); \
36+
if (sz == 32) \
37+
asm volatile("lw %0,0(%1)":"=r"(value):"r"(cmd_reg)); \
38+
else if (sz == 64) \
39+
asm volatile("ld %0,0(%1)":"=r"(value):"r"(cmd_reg)); \
40+
asm volatile("fence"); \
41+
return value; \
42+
}
43+
44+
#define CPS_ACCESSOR_W(unit, sz, base, off, name) \
45+
static inline void write_##unit##_##name(u32 hartid, u##sz value, bool local_p) \
46+
{ \
47+
long cmd_reg; \
48+
int cl, co; \
49+
cl = cpu_cluster(hartid); \
50+
co = cpu_core(hartid); \
51+
cmd_reg = (local_p ? (base) : ((base) - CM_BASE + GLOBAL_CM_BASE[cl])) \
52+
+ (co << CM_BASE_CORE_SHIFT) \
53+
+ off; \
54+
if (DEBUG_CM) \
55+
sbi_printf("CM WRITE%d cmd_reg=%lx value=%lx\n", sz, \
56+
cmd_reg, (unsigned long)value); \
57+
if (sz == 32) \
58+
asm volatile("sw %0,0(%1)"::"r"(value),"r"(cmd_reg)); \
59+
else if (sz == 64) \
60+
asm volatile("sd %0,0(%1)"::"r"(value),"r"(cmd_reg)); \
61+
asm volatile("fence"); \
62+
}
63+
64+
#define CPS_ACCESSOR_RW(unit, sz, base, off, name) \
65+
CPS_ACCESSOR_R(unit, sz, base, off, name) \
66+
CPS_ACCESSOR_W(unit, sz, base, off, name)
67+
68+
#define CPC_CX_ACCESSOR_RW(sz, off, name) \
69+
CPS_ACCESSOR_RW(cpc, sz, CPC_BASE, CPC_OFF_LOCAL + (off), co_##name)
70+
71+
#define GCR_CX_ACCESSOR_RW(sz, off, name) \
72+
CPS_ACCESSOR_RW(gcr, sz, CM_BASE, GCR_OFF_LOCAL + (off), co_##name)
73+
74+
GCR_CX_ACCESSOR_RW(64, cpu_hart(hartid) << CM_BASE_HART_SHIFT, reset_base)
75+
GCR_CX_ACCESSOR_RW(32, GCR_CORE_COH_EN, coherence)
76+
77+
CPC_CX_ACCESSOR_RW(32, CPC_Cx_VP_RUN, vp_run)
78+
CPC_CX_ACCESSOR_RW(32, CPC_Cx_VP_STOP, vp_stop)
79+
CPC_CX_ACCESSOR_RW(32, CPC_Cx_CMD, cmd)
80+
CPC_CX_ACCESSOR_RW(32, CPC_Cx_STAT_CONF, stat_conf)
81+
82+
#define CPC_ACCESSOR_RW(sz, off, name) \
83+
CPS_ACCESSOR_RW(cpc, sz, CPC_BASE, off, name)
84+
85+
CPC_ACCESSOR_RW(32, CPC_PWRUP_CTL, pwrup_ctl)
86+
CPC_ACCESSOR_RW(32, CPC_CM_STAT_CONF, cm_stat_conf)
87+
88+
#endif

‎platform/generic/include/mips/p8700.h‎

Lines changed: 113 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,113 @@
1+
/*
2+
* SPDX-License-Identifier: BSD-2-Clause
3+
*
4+
* Copyright (c) 2025 MIPS
5+
*
6+
*/
7+
8+
#ifndef __P8700_H__
9+
#define __P8700_H__
10+
11+
#include <mips/board.h>
12+
13+
/* PMA */
14+
#define CSR_MIPSPMACFG0 0x7e0
15+
#define CSR_MIPSPMACFG1 0x7e1
16+
#define CSR_MIPSPMACFG2 0x7e2
17+
#define CSR_MIPSPMACFG3 0x7e3
18+
#define CSR_MIPSPMACFG4 0x7e4
19+
#define CSR_MIPSPMACFG5 0x7e5
20+
#define CSR_MIPSPMACFG6 0x7e6
21+
#define CSR_MIPSPMACFG7 0x7e7
22+
#define CSR_MIPSPMACFG8 0x7e8
23+
#define CSR_MIPSPMACFG9 0x7e9
24+
#define CSR_MIPSPMACFG10 0x7ea
25+
#define CSR_MIPSPMACFG11 0x7eb
26+
#define CSR_MIPSPMACFG12 0x7ec
27+
#define CSR_MIPSPMACFG13 0x7ed
28+
#define CSR_MIPSPMACFG14 0x7ee
29+
#define CSR_MIPSPMACFG15 0x7ef
30+
31+
/* MIPS CCA */
32+
#define CCA_CACHE_ENABLE 0
33+
#define CCA_CACHE_DISABLE 2
34+
#define PMA_SPECULATION (1 << 3)
35+
36+
/* MIPS CSR */
37+
#define CSR_MIPSTVEC 0x7c0
38+
#define CSR_MIPSCONFIG0 0x7d0
39+
#define CSR_MIPSCONFIG1 0x7d1
40+
#define CSR_MIPSCONFIG2 0x7d2
41+
#define CSR_MIPSCONFIG3 0x7d3
42+
#define CSR_MIPSCONFIG4 0x7d4
43+
#define CSR_MIPSCONFIG5 0x7d5
44+
#define CSR_MIPSCONFIG6 0x7d6
45+
#define CSR_MIPSCONFIG7 0x7d7
46+
#define CSR_MIPSCONFIG8 0x7d8
47+
#define CSR_MIPSCONFIG9 0x7d9
48+
#define CSR_MIPSCONFIG10 0x7da
49+
#define CSR_MIPSCONFIG11 0x7db
50+
51+
#define MIPSCONFIG5_MTW 4
52+
53+
#define GEN_MASK(h, l) (((1ul << ((h) + 1 - (l))) - 1) << (l))
54+
#define EXT(val, mask) (((val) & (mask)) >> (__builtin_ffs(mask) - 1))
55+
56+
/*
57+
* We allocate the number of bits to encode clusters, cores, and harts
58+
* from the original mhartid to a new dense index.
59+
*/
60+
#define NUM_OF_BITS_FOR_CLUSTERS 4
61+
#define NUM_OF_BITS_FOR_CORES 12
62+
#define NUM_OF_BITS_FOR_HARTS 4
63+
64+
/* To get the field from new/hashed mhartid */
65+
#define NEW_CLUSTER_SHIFT (NUM_OF_BITS_FOR_CORES + NUM_OF_BITS_FOR_HARTS)
66+
#define NEW_CLUSTER_MASK ((1 << NUM_OF_BITS_FOR_CLUSTERS) - 1)
67+
#define NEW_CORE_SHIFT NUM_OF_BITS_FOR_HARTS
68+
#define NEW_CORE_MASK ((1 << NUM_OF_BITS_FOR_CORES) - 1)
69+
#define NEW_HART_MASK ((1 << NUM_OF_BITS_FOR_HARTS) - 1)
70+
#define cpu_cluster(i) (((i) >> NEW_CLUSTER_SHIFT) & NEW_CLUSTER_MASK)
71+
#define cpu_core(i) (((i) >> NEW_CORE_SHIFT) & NEW_CORE_MASK)
72+
#define cpu_hart(i) ((i) & NEW_HART_MASK)
73+
74+
#define CPC_BASE (CM_BASE + 0x8000)
75+
76+
#define SIZE_FOR_CPC_MTIME 0x10000 /* The size must be 2^order */
77+
#define AIA_BASE (CM_BASE + 0x40000)
78+
#define SIZE_FOR_AIA_M_MODE 0x20000 /* The size must be 2^order */
79+
#define P8700_ALIGN 0x10000
80+
81+
#define CM_BASE_HART_SHIFT 3
82+
#define CM_BASE_CORE_SHIFT 8
83+
#define CM_BASE_CLUSTER_SHIFT 19
84+
85+
/* GCR Block offsets */
86+
#define GCR_OFF_LOCAL 0x2000
87+
88+
#define GCR_BASE_OFFSET 0x0008
89+
#define GCR_CORE_COH_EN 0x00f8
90+
#define GCR_CORE_COH_EN_EN (0x1 << 0)
91+
92+
#define L2_PFT_CONTROL_OFFSET 0x0300
93+
#define L2_PFT_CONTROL_B_OFFSET 0x0308
94+
95+
/* CPC Block offsets */
96+
#define CPC_PWRUP_CTL 0x0030
97+
#define CPC_CM_STAT_CONF 0x1008
98+
99+
#define CPC_OFF_LOCAL 0x2000
100+
101+
#define CPC_Cx_VP_STOP 0x0020
102+
#define CPC_Cx_VP_RUN 0x0028
103+
#define CPC_Cx_CMD 0x0000
104+
105+
#define CPC_Cx_CMD_PWRUP 0x3
106+
#define CPC_Cx_CMD_RESET 0x4
107+
108+
#define CPC_Cx_STAT_CONF 0x0008
109+
#define CPC_Cx_STAT_CONF_SEQ_STATE GEN_MASK(22, 19)
110+
#define CPC_Cx_STAT_CONF_SEQ_STATE_U5 6
111+
#define CPC_Cx_STAT_CONF_SEQ_STATE_U6 7
112+
113+
#endif

‎platform/generic/mips/objects.mk‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
#
2+
# SPDX-License-Identifier: BSD-2-Clause
3+
#
4+
5+
ifeq ($(PLATFORM_RISCV_XLEN), 64)
6+
carray-platform_override_modules-$(CONFIG_PLATFORM_MIPS_P8700) += mips_p8700
7+
platform-objs-$(CONFIG_PLATFORM_MIPS_P8700) += mips/p8700.o
8+
endif

0 commit comments

Comments
 (0)