@@ -1102,32 +1102,44 @@ void sbi_pmu_exit(struct sbi_scratch *scratch)
11021102
11031103static void pmu_sse_enable (uint32_t event_id )
11041104{
1105- struct sbi_pmu_hart_state * phs = pmu_thishart_state_ptr ();
11061105 unsigned long irq_mask = sbi_pmu_irq_mask ();
11071106
1108- phs -> sse_enabled = true;
1109- csr_clear (CSR_MIDELEG , irq_mask );
11101107 csr_clear (CSR_MIP , irq_mask );
11111108 csr_set (CSR_MIE , irq_mask );
11121109}
11131110
11141111static void pmu_sse_disable (uint32_t event_id )
11151112{
1116- struct sbi_pmu_hart_state * phs = pmu_thishart_state_ptr ();
11171113 unsigned long irq_mask = sbi_pmu_irq_mask ();
11181114
11191115 csr_clear (CSR_MIE , irq_mask );
11201116 csr_clear (CSR_MIP , irq_mask );
1121- csr_set (CSR_MIDELEG , irq_mask );
1122- phs -> sse_enabled = false;
11231117}
11241118
11251119static void pmu_sse_complete (uint32_t event_id )
11261120{
11271121 csr_set (CSR_MIE , sbi_pmu_irq_mask ());
11281122}
11291123
1124+ static void pmu_sse_register (uint32_t event_id )
1125+ {
1126+ struct sbi_pmu_hart_state * phs = pmu_thishart_state_ptr ();
1127+
1128+ phs -> sse_enabled = true;
1129+ csr_clear (CSR_MIDELEG , sbi_pmu_irq_mask ());
1130+ }
1131+
1132+ static void pmu_sse_unregister (uint32_t event_id )
1133+ {
1134+ struct sbi_pmu_hart_state * phs = pmu_thishart_state_ptr ();
1135+
1136+ phs -> sse_enabled = false;
1137+ csr_set (CSR_MIDELEG , sbi_pmu_irq_mask ());
1138+ }
1139+
11301140static const struct sbi_sse_cb_ops pmu_sse_cb_ops = {
1141+ .register_cb = pmu_sse_register ,
1142+ .unregister_cb = pmu_sse_unregister ,
11311143 .enable_cb = pmu_sse_enable ,
11321144 .disable_cb = pmu_sse_disable ,
11331145 .complete_cb = pmu_sse_complete ,
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