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aswatermanaswaterman
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Merge pull request #539 from rogerchang23424/bitmanip
Add bitmanip test cases
2 parents ad33ed3 + 9c06101 commit 3bd02c8

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lines changed

‎isa/Makefile‎

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,10 @@ include $(src_dir)/rv64ua/Makefrag
1414
include $(src_dir)/rv64uf/Makefrag
1515
include $(src_dir)/rv64ud/Makefrag
1616
include $(src_dir)/rv64uzfh/Makefrag
17+
include $(src_dir)/rv64uzba/Makefrag
18+
include $(src_dir)/rv64uzbb/Makefrag
19+
include $(src_dir)/rv64uzbc/Makefrag
20+
include $(src_dir)/rv64uzbs/Makefrag
1721
include $(src_dir)/rv64si/Makefrag
1822
include $(src_dir)/rv64ssvnapot/Makefrag
1923
include $(src_dir)/rv64mi/Makefrag
@@ -26,6 +30,10 @@ include $(src_dir)/rv32ua/Makefrag
2630
include $(src_dir)/rv32uf/Makefrag
2731
include $(src_dir)/rv32ud/Makefrag
2832
include $(src_dir)/rv32uzfh/Makefrag
33+
include $(src_dir)/rv32uzba/Makefrag
34+
include $(src_dir)/rv32uzbb/Makefrag
35+
include $(src_dir)/rv32uzbc/Makefrag
36+
include $(src_dir)/rv32uzbs/Makefrag
2937
include $(src_dir)/rv32si/Makefrag
3038
include $(src_dir)/rv32mi/Makefrag
3139

@@ -50,10 +58,10 @@ vpath %.S $(src_dir)
5058
$(RISCV_OBJDUMP) $< > $@
5159

5260
%.out: %
53-
$(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@
61+
$(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
5462

5563
%.out32: %
56-
$(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr --misaligned $< 2> $@
64+
$(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
5765

5866
define compile_template
5967

@@ -86,6 +94,10 @@ $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
8694
$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
8795
$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
8896
$(eval $(call compile_template,rv32uzfh,-march=rv32g_zfh -mabi=ilp32))
97+
$(eval $(call compile_template,rv32uzba,-march=rv32g_zba -mabi=ilp32))
98+
$(eval $(call compile_template,rv32uzbb,-march=rv32g_zbb -mabi=ilp32))
99+
$(eval $(call compile_template,rv32uzbc,-march=rv32g_zbc -mabi=ilp32))
100+
$(eval $(call compile_template,rv32uzbs,-march=rv32g_zbs -mabi=ilp32))
89101
$(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
90102
$(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
91103
ifeq ($(XLEN),64)
@@ -96,6 +108,10 @@ $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
96108
$(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
97109
$(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
98110
$(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64))
111+
$(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64))
112+
$(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64))
113+
$(eval $(call compile_template,rv64uzbc,-march=rv64g_zbc -mabi=lp64))
114+
$(eval $(call compile_template,rv64uzbs,-march=rv64g_zbs -mabi=lp64))
99115
$(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64))
100116
$(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64))
101117
$(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64))

‎isa/rv32uzba/Makefrag‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
#=======================================================================
2+
# Makefrag for rv32uzba tests
3+
#-----------------------------------------------------------------------
4+
5+
rv32uzba_sc_tests = \
6+
sh1add \
7+
sh2add \
8+
sh3add \
9+
10+
rv32uzba_p_tests = $(addprefix rv32uzba-p-, $(rv32uzba_sc_tests))
11+
rv32uzba_v_tests = $(addprefix rv32uzba-v-, $(rv32uzba_sc_tests))
12+
rv32uzba_ps_tests = $(addprefix rv32uzba-ps-, $(rv32uzba_sc_tests))
13+
14+
spike_tests += $(rv32uzba_p_tests) $(rv32uzba_v_tests)

‎isa/rv32uzba/sh1add.S‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
# See LICENSE for license details.
2+
3+
#*****************************************************************************
4+
# sh1add.S
5+
#-----------------------------------------------------------------------------
6+
#
7+
# Test sh1add instruction.
8+
#
9+
10+
#include "riscv_test.h"
11+
#include "test_macros.h"
12+
13+
RVTEST_RV32U
14+
RVTEST_CODE_BEGIN
15+
16+
#-------------------------------------------------------------
17+
# Arithmetic tests
18+
#-------------------------------------------------------------
19+
20+
TEST_RR_OP( 2, sh1add, 0x00000000, 0x00000000, 0x00000000 );
21+
TEST_RR_OP( 3, sh1add, 0x00000003, 0x00000001, 0x00000001 );
22+
TEST_RR_OP( 4, sh1add, 0x0000000d, 0x00000003, 0x00000007 );
23+
24+
TEST_RR_OP( 5, sh1add, 0xffff8000, 0x00000000, 0xffff8000 );
25+
TEST_RR_OP( 6, sh1add, 0x00000000, 0x80000000, 0x00000000 );
26+
TEST_RR_OP( 7, sh1add, 0xffff8000, 0x80000000, 0xffff8000 );
27+
28+
TEST_RR_OP( 8, sh1add, 0x00007fff, 0x00000000, 0x00007fff );
29+
TEST_RR_OP( 9, sh1add, 0xfffffffe, 0x7fffffff, 0x00000000 );
30+
TEST_RR_OP( 10, sh1add, 0x00007ffd, 0x7fffffff, 0x00007fff );
31+
32+
TEST_RR_OP( 11, sh1add, 0x00007fff, 0x80000000, 0x00007fff );
33+
TEST_RR_OP( 12, sh1add, 0xffff7ffe, 0x7fffffff, 0xffff8000 );
34+
35+
TEST_RR_OP( 13, sh1add, 0xffffffff, 0x00000000, 0xffffffff );
36+
TEST_RR_OP( 14, sh1add, 0xffffffff, 0xffffffff, 0x00000001 );
37+
TEST_RR_OP( 15, sh1add, 0xfffffffd, 0xffffffff, 0xffffffff );
38+
39+
TEST_RR_OP( 16, sh1add, 0x80000001, 0x00000001, 0x7fffffff );
40+
41+
#-------------------------------------------------------------
42+
# Source/Destination tests
43+
#-------------------------------------------------------------
44+
45+
TEST_RR_SRC1_EQ_DEST( 17, sh1add, 37, 13, 11 );
46+
TEST_RR_SRC2_EQ_DEST( 18, sh1add, 39, 14, 11 );
47+
TEST_RR_SRC12_EQ_DEST( 19, sh1add, 39, 13 );
48+
49+
#-------------------------------------------------------------
50+
# Bypassing tests
51+
#-------------------------------------------------------------
52+
53+
TEST_RR_DEST_BYPASS( 20, 0, sh1add, 37, 13, 11 );
54+
TEST_RR_DEST_BYPASS( 21, 1, sh1add, 39, 14, 11 );
55+
TEST_RR_DEST_BYPASS( 22, 2, sh1add, 41, 15, 11 );
56+
57+
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh1add, 37, 13, 11 );
58+
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh1add, 39, 14, 11 );
59+
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh1add, 41, 15, 11 );
60+
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh1add, 37, 13, 11 );
61+
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh1add, 39, 14, 11 );
62+
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh1add, 41, 15, 11 );
63+
64+
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh1add, 37, 13, 11 );
65+
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh1add, 39, 14, 11 );
66+
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh1add, 41, 15, 11 );
67+
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh1add, 37, 13, 11 );
68+
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh1add, 39, 14, 11 );
69+
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh1add, 41, 15, 11 );
70+
71+
TEST_RR_ZEROSRC1( 35, sh1add, 15, 15 );
72+
TEST_RR_ZEROSRC2( 36, sh1add, 64, 32 );
73+
TEST_RR_ZEROSRC12( 37, sh1add, 0 );
74+
TEST_RR_ZERODEST( 38, sh1add, 16, 30 );
75+
76+
TEST_PASSFAIL
77+
78+
RVTEST_CODE_END
79+
80+
.data
81+
RVTEST_DATA_BEGIN
82+
83+
TEST_DATA
84+
85+
RVTEST_DATA_END

‎isa/rv32uzba/sh2add.S‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
# See LICENSE for license details.
2+
3+
#*****************************************************************************
4+
# sh2add.S
5+
#-----------------------------------------------------------------------------
6+
#
7+
# Test sh2add instruction.
8+
#
9+
10+
#include "riscv_test.h"
11+
#include "test_macros.h"
12+
13+
RVTEST_RV32U
14+
RVTEST_CODE_BEGIN
15+
16+
#-------------------------------------------------------------
17+
# Arithmetic tests
18+
#-------------------------------------------------------------
19+
20+
TEST_RR_OP( 2, sh2add, 0x00000000, 0x00000000, 0x00000000 );
21+
TEST_RR_OP( 3, sh2add, 0x00000005, 0x00000001, 0x00000001 );
22+
TEST_RR_OP( 4, sh2add, 0x00000013, 0x00000003, 0x00000007 );
23+
24+
TEST_RR_OP( 5, sh2add, 0xffff8000, 0x00000000, 0xffff8000 );
25+
TEST_RR_OP( 6, sh2add, 0x00000000, 0x80000000, 0x00000000 );
26+
TEST_RR_OP( 7, sh2add, 0xffff8000, 0x80000000, 0xffff8000 );
27+
28+
TEST_RR_OP( 8, sh2add, 0x00007fff, 0x00000000, 0x00007fff );
29+
TEST_RR_OP( 9, sh2add, 0xfffffffc, 0x7fffffff, 0x00000000 );
30+
TEST_RR_OP( 10, sh2add, 0x00007ffb, 0x7fffffff, 0x00007fff );
31+
32+
TEST_RR_OP( 11, sh2add, 0x00007fff, 0x80000000, 0x00007fff );
33+
TEST_RR_OP( 12, sh2add, 0xffff7ffc, 0x7fffffff, 0xffff8000 );
34+
35+
TEST_RR_OP( 13, sh2add, 0xffffffff, 0x00000000, 0xffffffff );
36+
TEST_RR_OP( 14, sh2add, 0xfffffffd, 0xffffffff, 0x00000001 );
37+
TEST_RR_OP( 15, sh2add, 0xfffffffb, 0xffffffff, 0xffffffff );
38+
39+
TEST_RR_OP( 16, sh2add, 0x80000003, 0x00000001, 0x7fffffff );
40+
41+
#-------------------------------------------------------------
42+
# Source/Destination tests
43+
#-------------------------------------------------------------
44+
45+
TEST_RR_SRC1_EQ_DEST( 17, sh2add, 63, 13, 11 );
46+
TEST_RR_SRC2_EQ_DEST( 18, sh2add, 67, 14, 11 );
47+
TEST_RR_SRC12_EQ_DEST( 19, sh2add, 65, 13 );
48+
49+
#-------------------------------------------------------------
50+
# Bypassing tests
51+
#-------------------------------------------------------------
52+
53+
TEST_RR_DEST_BYPASS( 20, 0, sh2add, 63, 13, 11 );
54+
TEST_RR_DEST_BYPASS( 21, 1, sh2add, 67, 14, 11 );
55+
TEST_RR_DEST_BYPASS( 22, 2, sh2add, 71, 15, 11 );
56+
57+
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh2add, 63, 13, 11 );
58+
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh2add, 67, 14, 11 );
59+
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh2add, 71, 15, 11 );
60+
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh2add, 63, 13, 11 );
61+
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh2add, 67, 14, 11 );
62+
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh2add, 71, 15, 11 );
63+
64+
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh2add, 63, 13, 11 );
65+
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh2add, 67, 14, 11 );
66+
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh2add, 71, 15, 11 );
67+
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh2add, 63, 13, 11 );
68+
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh2add, 67, 14, 11 );
69+
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh2add, 71, 15, 11 );
70+
71+
TEST_RR_ZEROSRC1( 35, sh2add, 15, 15 );
72+
TEST_RR_ZEROSRC2( 36, sh2add, 128, 32 );
73+
TEST_RR_ZEROSRC12( 37, sh2add, 0 );
74+
TEST_RR_ZERODEST( 38, sh2add, 16, 30 );
75+
76+
TEST_PASSFAIL
77+
78+
RVTEST_CODE_END
79+
80+
.data
81+
RVTEST_DATA_BEGIN
82+
83+
TEST_DATA
84+
85+
RVTEST_DATA_END

‎isa/rv32uzba/sh3add.S‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,85 @@
1+
# See LICENSE for license details.
2+
3+
#*****************************************************************************
4+
# sh3add.S
5+
#-----------------------------------------------------------------------------
6+
#
7+
# Test sh3add instruction.
8+
#
9+
10+
#include "riscv_test.h"
11+
#include "test_macros.h"
12+
13+
RVTEST_RV32U
14+
RVTEST_CODE_BEGIN
15+
16+
#-------------------------------------------------------------
17+
# Arithmetic tests
18+
#-------------------------------------------------------------
19+
20+
TEST_RR_OP( 2, sh3add, 0x00000000, 0x00000000, 0x00000000 );
21+
TEST_RR_OP( 3, sh3add, 0x00000009, 0x00000001, 0x00000001 );
22+
TEST_RR_OP( 4, sh3add, 0x0000001f, 0x00000003, 0x00000007 );
23+
24+
TEST_RR_OP( 5, sh3add, 0xffff8000, 0x00000000, 0xffff8000 );
25+
TEST_RR_OP( 6, sh3add, 0x00000000, 0x80000000, 0x00000000 );
26+
TEST_RR_OP( 7, sh3add, 0xffff8000, 0x80000000, 0xffff8000 );
27+
28+
TEST_RR_OP( 8, sh3add, 0x00007fff, 0x00000000, 0x00007fff );
29+
TEST_RR_OP( 9, sh3add, 0xfffffff8, 0x7fffffff, 0x00000000 );
30+
TEST_RR_OP( 10, sh3add, 0x00007ff7, 0x7fffffff, 0x00007fff );
31+
32+
TEST_RR_OP( 11, sh3add, 0x00007fff, 0x80000000, 0x00007fff );
33+
TEST_RR_OP( 12, sh3add, 0xffff7ff8, 0x7fffffff, 0xffff8000 );
34+
35+
TEST_RR_OP( 13, sh3add, 0xffffffff, 0x00000000, 0xffffffff );
36+
TEST_RR_OP( 14, sh3add, 0xfffffff9, 0xffffffff, 0x00000001 );
37+
TEST_RR_OP( 15, sh3add, 0xfffffff7, 0xffffffff, 0xffffffff );
38+
39+
TEST_RR_OP( 16, sh3add, 0x80000007, 0x00000001, 0x7fffffff );
40+
41+
#-------------------------------------------------------------
42+
# Source/Destination tests
43+
#-------------------------------------------------------------
44+
45+
TEST_RR_SRC1_EQ_DEST( 17, sh3add, 115, 13, 11 );
46+
TEST_RR_SRC2_EQ_DEST( 18, sh3add, 123, 14, 11 );
47+
TEST_RR_SRC12_EQ_DEST( 19, sh3add, 117, 13 );
48+
49+
#-------------------------------------------------------------
50+
# Bypassing tests
51+
#-------------------------------------------------------------
52+
53+
TEST_RR_DEST_BYPASS( 20, 0, sh3add, 115, 13, 11 );
54+
TEST_RR_DEST_BYPASS( 21, 1, sh3add, 123, 14, 11 );
55+
TEST_RR_DEST_BYPASS( 22, 2, sh3add, 131, 15, 11 );
56+
57+
TEST_RR_SRC12_BYPASS( 23, 0, 0, sh3add, 115, 13, 11 );
58+
TEST_RR_SRC12_BYPASS( 24, 0, 1, sh3add, 123, 14, 11 );
59+
TEST_RR_SRC12_BYPASS( 25, 0, 2, sh3add, 131, 15, 11 );
60+
TEST_RR_SRC12_BYPASS( 26, 1, 0, sh3add, 115, 13, 11 );
61+
TEST_RR_SRC12_BYPASS( 27, 1, 1, sh3add, 123, 14, 11 );
62+
TEST_RR_SRC12_BYPASS( 28, 2, 0, sh3add, 131, 15, 11 );
63+
64+
TEST_RR_SRC21_BYPASS( 29, 0, 0, sh3add, 115, 13, 11 );
65+
TEST_RR_SRC21_BYPASS( 30, 0, 1, sh3add, 123, 14, 11 );
66+
TEST_RR_SRC21_BYPASS( 31, 0, 2, sh3add, 131, 15, 11 );
67+
TEST_RR_SRC21_BYPASS( 32, 1, 0, sh3add, 115, 13, 11 );
68+
TEST_RR_SRC21_BYPASS( 33, 1, 1, sh3add, 123, 14, 11 );
69+
TEST_RR_SRC21_BYPASS( 34, 2, 0, sh3add, 131, 15, 11 );
70+
71+
TEST_RR_ZEROSRC1( 35, sh3add, 15, 15 );
72+
TEST_RR_ZEROSRC2( 36, sh3add, 256, 32 );
73+
TEST_RR_ZEROSRC12( 37, sh3add, 0 );
74+
TEST_RR_ZERODEST( 38, sh3add, 16, 30 );
75+
76+
TEST_PASSFAIL
77+
78+
RVTEST_CODE_END
79+
80+
.data
81+
RVTEST_DATA_BEGIN
82+
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TEST_DATA
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RVTEST_DATA_END

‎isa/rv32uzbb/Makefrag‎

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#=======================================================================
2+
# Makefrag for rv32uzbb tests
3+
#-----------------------------------------------------------------------
4+
5+
rv32uzbb_sc_tests = \
6+
andn \
7+
clz \
8+
cpop \
9+
ctz \
10+
max maxu \
11+
min minu \
12+
orc_b \
13+
orn \
14+
rev8 \
15+
rol \
16+
ror \
17+
rori \
18+
sext_b sext_h \
19+
xnor \
20+
zext_h \
21+
22+
rv32uzbb_p_tests = $(addprefix rv32uzbb-p-, $(rv32uzbb_sc_tests))
23+
rv32uzbb_v_tests = $(addprefix rv32uzbb-v-, $(rv32uzbb_sc_tests))
24+
rv32uzbb_ps_tests = $(addprefix rv32uzbb-ps-, $(rv32uzbb_sc_tests))
25+
26+
spike_tests += $(rv32uzbb_p_tests) $(rv32uzbb_v_tests)

‎isa/rv32uzbb/andn.S‎

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@@ -0,0 +1,7 @@
1+
# See LICENSE for license details.
2+
3+
#include "riscv_test.h"
4+
#undef RVTEST_RV64U
5+
#define RVTEST_RV64U RVTEST_RV32U
6+
7+
#include "../rv64uzbb/andn.S"

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