Merge pull request #624 from riscv-software-src/ziccid

Add Ziccid test

Author: aswaterman

isa/Makefile

@@ -13,6 +13,7 @@ include $(src_dir)/rv64um/Makefrag
 include $(src_dir)/rv64ua/Makefrag
 include $(src_dir)/rv64uf/Makefrag
 include $(src_dir)/rv64ud/Makefrag
+include $(src_dir)/rv64uziccid/Makefrag
 include $(src_dir)/rv64uzfh/Makefrag
 include $(src_dir)/rv64uzba/Makefrag
 include $(src_dir)/rv64uzbb/Makefrag
@@ -59,10 +60,10 @@ vpath %.S $(src_dir)
 	$(RISCV_OBJDUMP) $< > $@
 
 %.out: %
-	$(RISCV_SIM) --isa=rv64gch_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
+	$(RISCV_SIM) --isa=rv64gch_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
 
 %.out32: %
-	$(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
+	$(RISCV_SIM) --isa=rv32gc_ziccid_zfh_zicboz_svnapot_zicntr_zba_zbb_zbc_zbs --misaligned $< 2> $@
 
 define compile_template
 
@@ -108,6 +109,7 @@ $(eval $(call compile_template,rv64um,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
+$(eval $(call compile_template,rv64uziccid,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64))
 $(eval $(call compile_template,rv64uzba,-march=rv64g_zba -mabi=lp64))
 $(eval $(call compile_template,rv64uzbb,-march=rv64g_zbb -mabi=lp64))

isa/rv64uziccid/Makefrag

@@ -0,0 +1,9 @@
+#=======================================================================
+# Makefrag for rv64uziccid tests
+#-----------------------------------------------------------------------
+
+rv64uziccid_sc_tests = \
+	ziccid \
+
+rv64uziccid_p_tests = $(addprefix rv64uziccid-p-, $(rv64uziccid_sc_tests))
+rv64uziccid_v_tests = $(addprefix rv64uziccid-v-, $(rv64uziccid_sc_tests))

isa/rv64uziccid/ziccid.S

@@ -0,0 +1,48 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ziccid.S
+#-----------------------------------------------------------------------------
+#
+# Test Ziccid eventuality property.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  la t0, insn
+  li t1, 0x00100513   # li a0, 1
+  li t2, 0x00000513   # li a0, 0
+
+  sw t2, (t0)
+  fence.i
+
+  li a1, 100
+loop:
+  .balign 2
+insn:
+  .word 0
+
+  addi a1, a1, -1
+  bnez a1, 1f
+  # modify instruction on 100th iteration
+  sw t1, (t0)
+1:
+  # break out of loop if the modified instruction is executed
+  beqz a0, loop
+
+  TEST_CASE(2, x0, 0, nop)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END