Merge pull request #49 from riscv-software-src/crd-james

Crd james

Author: dhower-qc

.github/workflows/pages.yml

@@ -53,6 +53,8 @@ jobs:
       run: mkdir -p _site/manual
     - name: Create _site/pdfs
       run: mkdir -p _site/pdfs
+    - name: Create _site/htmls
+      run: mkdir -p _site/htmls
     - name: Copy cfg html
       run: cp -R gen/cfg_html_doc/generic_rv64/html _site/example_cfg
     - name: Create RVA Family PDF Spec
@@ -63,6 +65,10 @@ jobs:
       run: ./do gen:csc_crd_pdf[MC-1]
     - name: Copy MC-1 PDF
       run: cp gen/csc_crd_doc/pdf/MC-1.pdf _site/pdfs/MC-1.pdf
+    - name: Create MC-1 HTML Spec
+      run: ./do gen:csc_crd_html[MC-1]
+    - name: Copy MC-1 HTML
+      run: cp gen/csc_crd_doc/html/MC-1.html _site/htmls/MC-1.html
     - name: Copy manual html
       run: cp -R gen/manual/isa/top/all/html _site/manual
     - name: Setup Pages

README.adoc

@@ -29,9 +29,9 @@ This repository contains:
 
  * Generate https://riscv-software-src.github.io/riscv-unified-db/manual/index.html[configuration-specific documentation] taylored to the set of implemented extensions and unnamed implementation options (_e.g._, `./do gen:html[generic_rv64]`).
  ** Only implemented extensions/instructions/CSRs are included
- ** Unreachable/unimplmented parts of the formal specification are pruned away
+ ** Unreachable/unimplemented parts of the formal specification are pruned away
  ** A dedicated documentation page for every implemented instruction, including its encoding, pruned execution behavior, and what types of exceptions it may cause.
- ** A dedication documentation page for every implemented CSR, including its (possibly runtime-changing) encoding, fields, and pruned behavior on reads and writes
+ ** A dedicated documentation page for every implemented CSR, including its (possibly runtime-changing) encoding, fields, and pruned behavior on reads and writes
  ** Clickable links to all mentions of instructions, extensions, CSRs, CSR fields, and glossary terms.
  * Generate documentation for specific extensions (_e.g._, `./do gen:ext_pdf[B]`)
  ** Automatically include a complete list of added instructions and CSRs

arch/README.adoc

@@ -200,7 +200,7 @@ marchid: # <1>
   length: MXLEN # <4>
   description: | # <5>
     Asciidoc description
-  definedBy: I # <6>
+  definedBy: Sm # <6>
   fields: # <7>
     Architecture:
       location_rv32: 31-0 # <8>

arch/csc_crd/MC-1.yaml

@@ -32,19 +32,38 @@ MC-1:
     mandatory:
     - name: I
       version: "~> 2.1"
-      note: "The I extension is the base Integer instruction set and is considered an \"extension\" for convenience."
+    - name: C
+      version: "~> 2.2"
       param_constraints:
-          PRECISE_SYNCHRONOUS_EXCEPTIONS:
+          MUTABLE_MISA_C:
             schema:
-              const: true
-          TRAP_ON_UNIMPLEMENTED_CSR:
+              const: false
+    - name: M
+      version: "~> 2.0"
+    - name: Zicsr
+      version: "~> 2.0"
+    - name: Zicntr
+      version: "~> 2.0"
+    - name: Sm
+      version: "~> 1.11"
+      param_constraints:
+          MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
+          MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained
+          ARCH_ID: {} # Unconstrained
+          IMP_ID: {} # Unconstrained
+          VENDOR_ID_BANK: {} # Unconstrained
+          VENDOR_ID_OFFSET: {} # Unconstrained
+          MISA_CSR_IMPLEMENTED: {} # Unconstrained
+          TIME_CSR_IMPLEMENTED: {} # Unconstrained
+          MTVAL_WIDTH: {} # Unconstrained
+          PHYS_ADDR_WIDTH: {} # Unconstrained
+          PRECISE_SYNCHRONOUS_EXCEPTIONS:
             schema:
               const: true
-          TRAP_ON_UNIMPLEMENTED_INSTRUCTION:
+          TRAP_ON_ECALL_FROM_M:
             schema:
               const: true
-          TRAP_ON_ECALL_FROM_M:
-            note: REQ-UINST-017
+          TRAP_ON_EBREAK:
             schema:
               const: true
           REPORT_VA_IN_MTVAL_ON_BREAKPOINT:
@@ -65,41 +84,16 @@ MC-1:
           M_MODE_ENDIANESS:
             schema:
               const: little
-          # OPT-RDTIME doesn't need constraint (behavior defined by TIME_CSR_IMPLEMENTED)
-          # OPT-MTIME-PADDR doesn't have parameter -- it's considered non-ISA by the database
-          # OPT-MTIMECMP-PADDR doesn't have parameter -- it's considered non-ISA by the database
-          # OPT-MSIP-PADDR doesn't have parameter -- it's considered non-ISA by the database
-          # OPT-MHARTID doesn't need constrained (behavior is a builtin)
-          # OPT-MVENDORID doesn't need constrained (but behavior is controlled by VENDOR_ID_BANK and VENDOR_ID_OFFSET)
-          # OPT-MARCHID doesn't need constrained (but behavior is controlled by ARCH_ID)
-          # OPT-MIMPID doesn't need constrained (but behavior is controlled by IMP_ID)
-          # OPT-MISA doesn't need constrained (but behavior is controlled by MISA_CSR_IMPLEMENTED)
-          # OPT-CLINT doesn't need a parameter; it is mandated in the spec
-          # OPT-CLIC doesn't need a paramter
-          MTVEC_BASE_ALIGNMENT_DIRECT:
-            note: OPT-MTVEC-ALIGN-DIRECT
-            schema:
-              const: 4
-          MTVEC_BASE_ALIGNMENT_VECTORED:
-            note: OPT-MTVEV-ALIGN-VECTORED
-            schema:
-              const: 4
-          ARCH_ID: {} # Unconstrained
           XLEN:
             schema:
               const: 32
-    - name: C
-      version: "~> 2.2"
-    - name: M
-      version: "~> 2.0"
-    - name: Zicsr
-      version: "~> 2.0"
-    - name: Zicntr
-      version: "~> 2.0"
+          CONFIG_PTR_ADDRESS:
+            schema:
+              const: 0
     #XXX optional: {} # None
     optional:
-    - name: B
-      note: "This is just for testing. B isn't really optional for MC-1."
+    - name: Zifencei
+      note: "This is just for testing. Zifencei extension isn't really optional for MC-1."
 
   requirement_groups:
     - name: MC-Unpriv
@@ -147,3 +141,11 @@ MC-1:
         description: Should return the most-significant 32-bits of the `mcycle` CSR when reading `cycleh`
       - name: REQ-M32CSR-002
         description: Should return the most-significant 32-bits of the `minstret` CSR when reading `instreth`
+
+    - name: MC-Priv
+      description: |
+        The MC-Priv defines Privileged ISA requirements.
+      requirements:
+      - name: REQ-PRIV-HARTID
+        description: | 
+          One hart in system has to have a HARTID of 0. Reading `mhartid` on other CSRs provides some value.

arch/csr/I/pmpaddr0.yaml

@@ -10,7 +10,7 @@ pmpaddr0:
   priv_mode: M
   length: MXLEN
   description: PMP entry address
-  definedBy: I
+  definedBy: Sm
   fields:
     ADDR:
       location_rv32: 31-0

arch/csr/I/pmpaddr1.yaml

@@ -10,7 +10,7 @@ pmpaddr1:
   priv_mode: M
   length: MXLEN
   description: PMP entry address
-  definedBy: I
+  definedBy: Sm
   fields:
     ADDR:
       location_rv32: 31-0

arch/csr/I/pmpaddr10.yaml

@@ -10,7 +10,7 @@ pmpaddr10:
   priv_mode: M
   length: MXLEN
   description: PMP entry address
-  definedBy: I
+  definedBy: Sm
   fields:
     ADDR:
       location_rv32: 31-0

arch/csr/I/pmpaddr11.yaml

@@ -10,7 +10,7 @@ pmpaddr11:
   priv_mode: M
   length: MXLEN
   description: PMP entry address
-  definedBy: I
+  definedBy: Sm
   fields:
     ADDR:
       location_rv32: 31-0

arch/csr/I/pmpaddr12.yaml

@@ -10,7 +10,7 @@ pmpaddr12:
   priv_mode: M
   length: MXLEN
   description: PMP entry address
-  definedBy: I
+  definedBy: Sm
   fields:
     ADDR:
       location_rv32: 31-0

arch/csr/I/pmpaddr13.yaml

@@ -10,7 +10,7 @@ pmpaddr13:
   priv_mode: M
   length: MXLEN
   description: PMP entry address
-  definedBy: I
+  definedBy: Sm
   fields:
     ADDR:
       location_rv32: 31-0