Misc. fixes to generators and Xqci extensions fixes (#551)

* Xqci/Xqcibm extension: fix some representation issues, fix qc.extdur rs1 != 31

Signed-off-by: Albert Yosher <[email protected]>

* Xqci: fix asciidoc formatting in description

* gen:adoc fix asciidoc generation of IDL csr read

* gen:ext_pdf fix implication list; improve version display

* Add missing word 'CSRs' in CSR summary generation

Signed-off-by: Albert Yosher <[email protected]>

---------

Signed-off-by: Albert Yosher <[email protected]>
Co-authored-by: Albert Yosher <[email protected]>

Author: dhower-qc

arch_overlay/qc_iu/ext/Xqci.yaml

@@ -242,7 +242,7 @@ versions:
     - Fix rs1 cannot be 31 for qc.extdu, qc.extd, qc.extdur, instructions
     - Fix rs1 cannot be 31 for qc.extduprh, qc.extdprh, qc.extdupr, qc.extdr qc.extdpr instructions
     - Fix typos in IDL code (missing ')' ) for qc.extdpr, qc.extdr instructions
-    - Fix IDL code to look correct in PDF for qc.insbhr and qc.insbh instructions
+    - Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions
     - Fix Xqci extension description to reflect correct 48-bit format field names
     - Fix IDL code to to match description for qc.insbr instruction
     - Add stack checks to qc.c.mienter, qc.c.mienter.nest, qc.c.mileaveret
@@ -330,7 +330,7 @@ description: |
   QC.EAI format used for 48-bit instructions that operate on 32-bit immediate argument.
   --
 
-  [%autowidth, cols="4*", options="header" }
+  [%autowidth, cols="4*", options="header" ]
   |===
   ^|Field
   ^|Start bit
@@ -367,7 +367,7 @@ description: |
   QC.EI format used for 48-bit instructions that operate on 26-bit immediate argument, including loads.
   --
 
-  [%autowidth, cols="4*", options="header" }
+  [%autowidth, cols="4*", options="header" ]
   |===
   ^|Field
   ^|Start bit
@@ -414,7 +414,7 @@ description: |
   QC.EB format used for 48-bit branch instructions that compare register with 16-bit immediate.
   --
 
-  [%autowidth, cols="4*", options="header" }
+  [%autowidth, cols="4*", options="header" ]
   |===
   ^|Field
   ^|Start bit
@@ -461,7 +461,7 @@ description: |
   QC.EJ format used for 48-bit jump/call instructions with 32-bit immediate target address.
   --
 
-  [%autowidth, cols="4*", options="header" }
+  [%autowidth, cols="4*", options="header" ]
   |===
   ^|Field
   ^|Start bit

arch_overlay/qc_iu/ext/Xqcibm.yaml

@@ -85,7 +85,7 @@ versions:
     - Fix rs1 cannot be 31 for qc.extdu, qc.extd, qc.extdur, instructions
     - Fix rs1 cannot be 31 for qc.extduprh, qc.extdprh, qc.extdupr, qc.extdr qc.extdpr instructions
     - Fix typos in IDL code (missing ')' ) for qc.extdpr, qc.extdr instructions
-    - Fix IDL code to look correct in PDF for qc.insbhr and qc.insbh instructions
+    - Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions
     - Fix IDL code to to match description for qc.insbr instruction
   requires: { name: Zca, version: ">= 1.0.0" }
 description: |

arch_overlay/qc_iu/inst/Xqci/qc.extdur.yaml

@@ -24,6 +24,7 @@ encoding:
       not: 0
     - name: rs1
       location: 19-15
+      not: 31
     - name: rd
       location: 11-7
       not: 0

arch_overlay/qc_iu/inst/Xqci/qc.insbh.yaml

@@ -12,7 +12,7 @@ description: |
   higher part using QC32.INSBH.
   The width of the subset is determined by (`width_minus1` + 1) (1..32),
   and the offset of the subset is determined by `shamt`.
-  In case when width + offset <= 32, the destination register is left unchanged.
+  In case when width + offset < 33, the destination register is left unchanged.
   Instruction encoded in I instruction format.
 definedBy:
   anyOf:

arch_overlay/qc_iu/inst/Xqci/qc.insbhr.yaml

@@ -12,7 +12,7 @@ description: |
   higher part using QC32.INSBHR.
   The width of the subset is determined by `rs2` bits [21:16] (0..32),
   and the offset of the subset is determined by `rs2` bits [4:0].
-  In case when width + offset <= 32 or width == 0, the destination register is left unchanged.
+  In case when width + offset < 33 or width == 0, the destination register is left unchanged.
   In case when `rs2` bit [21] == 1 width is enforced to 32.
   Instruction encoded in R instruction format.
 definedBy:

backends/ext_pdf_doc/templates/ext_pdf.adoc.erb

@@ -154,8 +154,9 @@ This specification documents version <%= max_version.version_spec %> of <%= ext.
 === Version History
 
 <%- ext.versions.each do |version| -%>
+==== <%= version.version_spec %>
+
 --
-Version:: <%= version.version_spec %>
 State:: <%= version.state %>
 <%- unless version.ratification_date.nil? -%>
 Ratification Date:: <%= version.ratification_date %>
@@ -173,7 +174,9 @@ Changes::
 <%- end -%>
 <%- unless version.implications.empty? -%>
 Implies::
-<%= version.implications.each { |i| "* #{i[:ext_ver].name} (#{i[:ext_ver].version_spec}) #{i[:cond].empty? ? '' : i[:cond].to_asciidoc(join: ', ')}" }.join("\n* ") %>
+
+<%= version.implications.map { |i| "    * #{i[:ext_ver].name} (#{i[:ext_ver].version_spec}) #{i[:cond].empty? ? '' : i[:cond].to_asciidoc(join: ', ')}" }.join("\n") %>
+
 <%- unless version.requirement_condition.empty? -%>
 Requires::
 <%= version.requirement_condition.to_asciidoc %>
@@ -281,7 +284,7 @@ The following <%= ext.instructions.size %> instructions are affected by this ext
 
 <%- csr_list = ext.csrs.select { |csr| versions.any? { |ext_ver| csr.affected_by?(ext_ver) } } -%>
 
-The following <%= csr_list.size %> are affected by this extension.
+The following <%= csr_list.size %> CSRs are affected by this extension.
 
 [%autowidth]
 |===

lib/idl/passes/gen_adoc.rb

@@ -299,22 +299,22 @@ def gen_adoc(indent = 0, indent_spaces: 2)
 
   class CsrReadExpressionAst
     def gen_adoc(indent = 0, indent_spaces: 2)
-      idx_text =
-        if @idx.is_a?(AstNode)
-          @idx.text_value
+      idx =
+        if @idx_expr.nil?
+          @idx_text
         else
-          @idx
+          @idx_expr.gen_adoc(0)
         end
 
-      csr_text = "CSR[#{idx_text}]"
+      csr_text = "CSR[#{idx}]"
       if idx_text =~ /[0-9]+/
         # we don't have the symtab to map this to a csr name
         "#{' '*indent}#{csr_text}"
       else
         if @cfg_arch.csr(csr_text).nil?
           "#{' '*indent}#{csr_text}"
         else
-          "#{' '*indent}%%LINK%csr;#{idx_text};#{csr_text}%%"
+          "#{' '*indent}%%LINK%csr;#{idx};#{csr_text}%%"
         end
       end
     end