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james-ball-qualcommjames-ball-qualcomm
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Merge branch 'crd-james' of https://github.com/riscv-software-src/riscv-unified-db into crd-james
2 parents 2e7079c + 6cb9c2b commit 066b99e

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‎Gemfile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,4 +23,5 @@ group :development do
2323
gem "solargraph"
2424
gem 'rubocop-minitest'
2525
gem 'ruby-prof'
26+
gem "ruby-prof-flamegraph"
2627
end

‎Gemfile.lock‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,9 @@ GEM
107107
rubocop-minitest (0.35.1)
108108
rubocop (>= 1.61, < 2.0)
109109
rubocop-ast (>= 1.31.1, < 2.0)
110-
ruby-prof (1.7.0)
110+
ruby-prof (0.18.0)
111+
ruby-prof-flamegraph (0.3.0)
112+
ruby-prof (~> 0.13)
111113
ruby-progressbar (1.13.0)
112114
ruby-rc4 (0.1.5)
113115
simpleidn (0.2.3)
@@ -152,6 +154,7 @@ DEPENDENCIES
152154
rouge
153155
rubocop-minitest
154156
ruby-prof
157+
ruby-prof-flamegraph
155158
ruby-progressbar (~> 1.13)
156159
solargraph
157160
treetop (= 1.6.12)

‎Rakefile‎

Lines changed: 80 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
11
# frozen_string_literal: true
22

3+
require "etc"
4+
35
$root = Pathname.new(__FILE__).dirname.realpath
46
$lib = $root / "lib"
57

@@ -82,45 +84,84 @@ namespace :validate do
8284
end
8385
puts "All files validate against their schema"
8486
end
85-
task idl: "gen:arch" do
86-
puts "Type checking IDL code..."
87-
arch_def = arch_def_for("_")
88-
progressbar = ProgressBar.create(title: "Instructions", total: arch_def.instructions.size)
89-
arch_def.instructions.each do |inst|
90-
progressbar.increment
91-
inst.type_checked_operation_ast(arch_def.idl_compiler, arch_def.sym_table_32, 32) if inst.rv32?
92-
inst.type_checked_operation_ast(arch_def.idl_compiler, arch_def.sym_table_64, 64) if inst.rv64?
93-
# also need to check for an RV64 machine running with effective XLEN of 32
94-
inst.type_checked_operation_ast(arch_def.idl_compiler, arch_def.sym_table_64, 32) if inst.rv64? && inst.rv32?
95-
end
96-
progressbar = ProgressBar.create(title: "CSRs", total: arch_def.csrs.size)
97-
arch_def.csrs.each do |csr|
98-
progressbar.increment
99-
if csr.has_custom_sw_read?
100-
csr.type_checked_sw_read_ast(arch_def.sym_table_32) if csr.defined_in_base32?
101-
csr.type_checked_sw_read_ast(arch_def.sym_table_64) if csr.defined_in_base64?
102-
end
103-
csr.fields.each do |field|
104-
unless field.type_ast(arch_def.idl_compiler).nil?
105-
field.type_checked_type_ast(arch_def.sym_table_32) if csr.defined_in_base32? && field.defined_in_base32?
106-
field.type_checked_type_ast(arch_def.sym_table_64) if csr.defined_in_base64? && field.defined_in_base64?
107-
end
108-
unless field.reset_value_ast(arch_def.idl_compiler).nil?
109-
field.type_checked_reset_value_ast(arch_def.sym_table_32) if csr.defined_in_base32? && field.defined_in_base32?
110-
field.type_checked_reset_value_ast(arch_def.sym_table_64) if csr.defined_in_base64? && field.defined_in_base64?
111-
end
112-
unless field.sw_write_ast(arch_def.idl_compiler).nil?
113-
field.type_checked_sw_write_ast(arch_def.sym_table_32, 32) if csr.defined_in_base32? && field.defined_in_base32?
114-
field.type_checked_sw_write_ast(arch_def.sym_table_64, 64) if csr.defined_in_base64? && field.defined_in_base64?
115-
end
116-
end
117-
end
118-
progressbar = ProgressBar.create(title: "Functions", total: arch_def.functions.size)
119-
arch_def.functions.each do |func|
120-
progressbar.increment
121-
func.type_check_body(arch_def.sym_table_32)
122-
func.type_check_body(arch_def.sym_table_64)
123-
end
87+
task idl: ["gen:arch", "#{$root}/.stamps/arch-gen-_32.stamp", "#{$root}/.stamps/arch-gen-_64.stamp"] do
88+
print "Parsing IDL code for RV32..."
89+
arch_def_32 = arch_def_for("_32")
90+
puts "done"
91+
92+
arch_def_32.type_check
93+
94+
print "Parsing IDL code for RV64..."
95+
arch_def_64 = arch_def_for("_64")
96+
puts "done"
97+
98+
arch_def_64.type_check
99+
100+
# arch_def_64 = arch_def_for("_64")
101+
# arch_def_64.type_check
102+
103+
# puts "Type checking IDL code..."
104+
# progressbar = ProgressBar.create(title: "Instructions", total: arch_def_32.instructions.size + arch_def_64.instructions.size)
105+
# arch_def_32.instructions.each do |inst|
106+
# progressbar.increment
107+
# inst.type_checked_operation_ast(arch_def_32.idl_compiler, arch_def_32.symtab, 32) if inst.rv32?
108+
# end
109+
# arch_def_64.instructions.each do |inst|
110+
# progressbar.increment
111+
# inst.type_checked_operation_ast(arch_def_64.idl_compiler, arch_def_64.symtab, 64) if inst.rv64?
112+
# # also need to check for an RV64 machine running with effective XLEN of 32
113+
# inst.type_checked_operation_ast(arch_def_64.idl_compiler, arch_def_64.symtab, 32) if inst.rv64? && inst.rv32?
114+
# end
115+
116+
# progressbar = ProgressBar.create(title: "CSRs", total: arch_def_32.csrs.size + arch_def_64.csrs.size)
117+
# arch_def_32.csrs.each do |csr|
118+
# progressbar.increment
119+
# profile = RubyProf::Profile.new
120+
# result = profile.profile do
121+
# if csr.has_custom_sw_read?
122+
# csr.type_checked_sw_read_ast(arch_def_32.symtab) if csr.defined_in_base32?
123+
# end
124+
# csr.fields.each do |field|
125+
# unless field.type_ast(arch_def_32.symtab).nil?
126+
# field.type_checked_type_ast(arch_def_32.symtab) if csr.defined_in_base32? && field.defined_in_base32?
127+
# end
128+
# unless field.reset_value_ast(arch_def_32.symtab).nil?
129+
# field.type_checked_reset_value_ast(arch_def_32.symtab) if csr.defined_in_base32? && field.defined_in_base32?
130+
# end
131+
# unless field.sw_write_ast(arch_def_32.symtab).nil?
132+
# field.type_checked_sw_write_ast(arch_def_32.symtab, 32) if csr.defined_in_base32? && field.defined_in_base32?
133+
# end
134+
# end
135+
# end
136+
# RubyProf::GraphHtmlPrinter.new(result).print(File.open("#{csr.name}-prof.html", "w+"), {})
137+
# end
138+
# arch_def_64.csrs.each do |csr|
139+
# progressbar.increment
140+
# if csr.has_custom_sw_read?
141+
# csr.type_checked_sw_read_ast(arch_def_64.symtab) if csr.defined_in_base64?
142+
# end
143+
# csr.fields.each do |field|
144+
# unless field.type_ast(arch_def_64.symtab).nil?
145+
# field.type_checked_type_ast(arch_def_64.symtab) if csr.defined_in_base64? && field.defined_in_base64?
146+
# end
147+
# unless field.reset_value_ast(arch_def_64.symtab).nil?
148+
# field.type_checked_reset_value_ast(arch_def_64.symtab) if csr.defined_in_base64? && field.defined_in_base64?
149+
# end
150+
# unless field.sw_write_ast(arch_def_64.symtab).nil?
151+
# field.type_checked_sw_write_ast(arch_def_64.symtab, 32) if csr.defined_in_base32? && field.defined_in_base32?
152+
# field.type_checked_sw_write_ast(arch_def_64.symtab, 64) if csr.defined_in_base64? && field.defined_in_base64?
153+
# end
154+
# end
155+
# end
156+
# progressbar = ProgressBar.create(title: "Functions", total: arch_def_32.functions.size + arch_def_64.functions.size)
157+
# arch_def_32.functions.each do |func|
158+
# progressbar.increment
159+
# func.type_check(arch_def_32.symtab)
160+
# end
161+
# arch_def_64.functions.each do |func|
162+
# progressbar.increment
163+
# func.type_check(arch_def_64.symtab)
164+
# end
124165
puts "All IDL passed type checking"
125166
end
126167
end

‎arch/csr/H/htinst.yaml‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
3+
htinst:
4+
address: 0x64a
5+
long_name: Hypervisor Trap Instruction Register
6+
description: |
7+
When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero,
8+
provides information about the instruction that trapped, to assist software in handling the trap.
9+
The values that may be written to mtinst on a trap are documented in TODO.
10+
11+
htinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap.
12+
priv_mode: S
13+
length: SXLEN
14+
definedBy: H
15+
fields:
16+
VALUE:
17+
location_rv64: 63-0
18+
location_rv32: 31-0
19+
type(): |
20+
if ( (TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT != "always zero")
21+
|| (TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT != "always zero")
22+
|| (TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT != "always zero")
23+
|| (TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED != "always zero")
24+
|| (TINST_VALUE_ON_BREAKPOINT != "always zero")
25+
|| (TINST_VALUE_ON_VIRTUAL_INSTRUCTION != "always zero")
26+
|| (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
27+
|| (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
28+
|| (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
29+
|| (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
30+
|| (TINST_VALUE_ON_UCALL != "always zero")
31+
|| (TINST_VALUE_ON_SCALL != "always zero")
32+
|| (TINST_VALUE_ON_MCALL != "always zero")
33+
|| (TINST_VALUE_ON_VSCALL != "always zero")
34+
|| (TINST_VALUE_ON_LOAD_PAGE_FAULT != "always zero")
35+
|| (TINST_VALUE_ON_STORE_AMO_PAGE_FAULT != "always zero")) {
36+
return CsrFieldType::RWH;
37+
} else {
38+
return CsrFieldType::RO;
39+
}
40+
description: |
41+
Exception-speicific information for a trap into HS-mode.
42+
reset_value: UNDEFINED_LEGAL

‎arch/csr/H/htval.yaml‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
3+
htval:
4+
address: 0x643
5+
long_name: Hypervisor Trap Value Register
6+
description: |
7+
When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap.
8+
9+
When a guest-page-fault trap is taken into HS-mode, htval is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, htval is set to zero, but a future standard or extension may redefine htval's setting for other traps.
10+
11+
A guest-page fault may arise due to an implicit memory access during first-stage (VS-stage) address translation, in which case a guest physical address written to htval is that of the implicit memory access that faulted-for example, the address of a VS-level page table entry that could not be read. (The guest physical address corresponding to the original virtual address is unknown when VS-stage translation fails to complete.) Additional information is provided in CSR htinst to disambiguate such situations.
12+
13+
Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in htval corresponds to the faulting portion of the access as indicated by the virtual address in stval. For instruction guest-page faults on systems with variable-length instructions, a nonzero htval corresponds to the faulting portion of the instruction as indicated by the virtual address in stval.
14+
15+
htval is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.
16+
priv_mode: M
17+
length: MXLEN
18+
definedBy: H
19+
fields:
20+
VALUE:
21+
location_rv64: 63-0
22+
location_rv32: 31-0
23+
type(): |
24+
if (REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT
25+
|| REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT
26+
|| REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT
27+
|| REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT) {
28+
return CsrFieldType::RWH;
29+
} else {
30+
return CsrFieldType::RO;
31+
}
32+
description: |
33+
Exception-speicific information for a trap into M-mode.
34+
reset_value: UNDEFINED_LEGAL

‎arch/csr/H/mtinst.yaml‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
3+
mtinst:
4+
address: 0x34a
5+
long_name: Machine Trap Instruction Register
6+
description: |
7+
When a trap is taken into M-mode, mtinst is written with a value that, if nonzero,
8+
provides information about the instruction that trapped, to assist software in handling the trap.
9+
The values that may be written to mtinst on a trap are documented in TODO.
10+
11+
mtinst is a WARL register that need only be able to hold the values that the implementation may automatically write to it on a trap.
12+
priv_mode: M
13+
length: MXLEN
14+
definedBy: H
15+
fields:
16+
VALUE:
17+
location_rv64: 63-0
18+
location_rv32: 31-0
19+
type(): |
20+
if ( (TINST_VALUE_ON_FINAL_LOAD_GUEST_PAGE_FAULT != "always zero")
21+
|| (TINST_VALUE_ON_FINAL_STORE_AMO_GUEST_PAGE_FAULT != "always zero")
22+
|| (TINST_VALUE_ON_FINAL_INSTRUCTION_GUEST_PAGE_FAULT != "always zero")
23+
|| (TINST_VALUE_ON_INSTRUCTION_ADDRESS_MISALIGNED != "always zero")
24+
|| (TINST_VALUE_ON_BREAKPOINT != "always zero")
25+
|| (TINST_VALUE_ON_VIRTUAL_INSTRUCTION != "always zero")
26+
|| (TINST_VALUE_ON_LOAD_ADDRESS_MISALIGNED != "always zero")
27+
|| (TINST_VALUE_ON_LOAD_ACCESS_FAULT != "always zero")
28+
|| (TINST_VALUE_ON_STORE_AMO_ADDRESS_MISALIGNED != "always zero")
29+
|| (TINST_VALUE_ON_STORE_AMO_ACCESS_FAULT != "always_zero")
30+
|| (TINST_VALUE_ON_UCALL != "always zero")
31+
|| (TINST_VALUE_ON_SCALL != "always zero")
32+
|| (TINST_VALUE_ON_MCALL != "always zero")
33+
|| (TINST_VALUE_ON_VSCALL != "always zero")
34+
|| (TINST_VALUE_ON_LOAD_PAGE_FAULT != "always zero")
35+
|| (TINST_VALUE_ON_STORE_AMO_PAGE_FAULT != "always zero")) {
36+
return CsrFieldType::RWH;
37+
} else {
38+
return CsrFieldType::RO;
39+
}
40+
description: |
41+
Exception-speicific information for a trap into M-mode.
42+
reset_value: UNDEFINED_LEGAL

‎arch/csr/H/mtval2.yaml‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
2+
3+
mtval2:
4+
address: 0x34b
5+
long_name: Machine Second Trap Value Register
6+
description: |
7+
When a trap is taken into M-mode from a virtual mode, mtval2 is written with additional exception-specific information,
8+
alongside mtval, to assist software in handling the trap.
9+
10+
When a guest-page-fault trap is taken into M-mode, mtval2 is written with either zero or the guest physical address that faulted, shifted right by 2 bits. For other traps, mtval2 is set to zero, but a future standard or extension may redefine mtval2's setting for other traps.
11+
12+
If a guest-page fault is due to an implicit memory access during first-stage (VS-stage) address translation, a guest physical address written to mtval2 is that of the implicit memory access that faulted. Additional information is provided in CSR mtinst to disambiguate such situations.
13+
14+
Otherwise, for misaligned loads and stores that cause guest-page faults, a nonzero guest physical address in mtval2 corresponds to the faulting portion of the access as indicated by the virtual address in mtval. For instruction guest-page faults on systems with variable-length instructions, a nonzero mtval2 corresponds to the faulting portion of the instruction as indicated by the virtual address in mtval.
15+
16+
mtval2 is a WARL register that must be able to hold zero and may be capable of holding only an arbitrary subset of other 2-bit-shifted guest physical addresses, if any.
17+
priv_mode: M
18+
length: MXLEN
19+
definedBy: H
20+
fields:
21+
VALUE:
22+
location_rv64: 63-0
23+
location_rv32: 31-0
24+
type(): |
25+
if (REPORT_GPA_IN_TVAL_ON_LOAD_GUEST_PAGE_FAULT
26+
|| REPORT_GPA_IN_TVAL_ON_STORE_AMO_GUEST_PAGE_FAULT
27+
|| REPORT_GPA_IN_TVAL_ON_INSTRUCTION_GUEST_PAGE_FAULT
28+
|| REPORT_GPA_IN_TVAL_ON_INTERMEDIATE_GUEST_PAGE_FAULT) {
29+
return CsrFieldType::RWH;
30+
} else {
31+
return CsrFieldType::RO;
32+
}
33+
description: |
34+
Exception-speicific information for a trap into M-mode.
35+
reset_value: UNDEFINED_LEGAL

‎arch/csr/H/vsatp.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# yaml-language-server: $schema=../../schemas/csr_schema.json
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
22

33
vsatp:
44
address: 0x280
@@ -94,7 +94,7 @@ vsatp:
9494
return UNDEFINED_LEGAL_DETERMINISTIC;
9595
}
9696
} else {
97-
XReg shamt = (CSR[mstatus].SXL == $bits(XRegWidth::XLEN64)) ? 16 : 9;
97+
XReg shamt = ((XLEN == 32) || (CSR[mstatus].SXL == $bits(XRegWidth::XLEN32))) ? 9 : 16;
9898
XReg all_ones = ((1 << shamt) - 1);
9999
XReg largest_allowed_asid = (1 << shamt) - 1;
100100

‎arch/csr/cycleh.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ cycleh:
2727
fields:
2828
COUNT:
2929
location: 31-0
30-
alias: mcycleh.COUNT
30+
alias: mcycleh.COUNT[63:32]
3131
description: Alias of `mcycleh.COUNT`.
3232
type: RO-H
3333
reset_value: UNDEFINED_LEGAL

‎arch/csr/misa.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ misa:
9090
G:
9191
location: 6
9292
description: |
93-
Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, 'D'.
93+
Indicates support for all of the following extensions: `I`, `A`, `M`, `F`, `D`.
9494
type(): |
9595
if ((implemented?(ExtensionName::A) && MUTABLE_MISA_A) ||
9696
(implemented?(ExtensionName::M) && MUTABLE_MISA_M) ||

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