Added previously created operations description by dhower

Signed-off-by: Afonso Oliveira <[email protected]>

Author: AFOliveira

arch/inst/F/fclass.s.yaml

@@ -45,4 +45,29 @@ fclass.s:
     vu: always
   data_independent_timing: false
   operation(): |
-        
+    check_f_ok();
+
+    Bits<32> sp_value = f[fs1][31:0];
+
+    if (is_sp_neg_inf?(sp_value)) {
+      X[rd] = 1 << 0;
+    } else if (is_sp_neg_norm?(sp_value)) {
+      X[rd] = 1 << 1;
+    } else if (is_sp_neg_subnorm?(sp_value)) {
+      X[rd] = 1 << 2;
+    } else if (is_sp_neg_zero?(sp_value)) {
+      X[rd] = 1 << 3;
+    } else if (is_sp_pos_zero?(sp_value)) {
+      X[rd] = 1 << 4;
+    } else if (is_sp_pos_subnorm?(sp_value)) {
+      X[rd] = 1 << 5;
+    } else if (is_sp_pos_norm?(sp_value)) {
+      X[rd] = 1 << 6;
+    } else if (is_sp_pos_inf?(sp_value)) {
+      X[rd] = 1 << 7;
+    } else if (is_sp_signaling_nan?(sp_value)) {
+      X[rd] = 1 << 8;
+    } else {
+      assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value");
+      X[rd] = 1 << 9;
+    }        

arch/inst/F/fcvt.s.w.yaml

@@ -31,5 +31,20 @@ fcvt.s.w:
     vu: always
   data_independent_timing: false
   operation(): |
+    check_f_ok();
+
+    Bits<32> int_value = X[rs1];
+
+    Bits<1> sign = int_value[31];
+
+    RoundingMode rouding_mode = rm_to_mode(rm, $encoding);
+
+    if (! (int_value & 32'h7fff_ffff)) {
+      X[fd] = (sign == 1) ? packToF32UI(1, 0x9E, 0) : 0;
+    } else {
+      Bits<32> absA = (sign == 1) ? -int_value : int_value;
+      X[fd] = softfloat_normRoundPackToF32( sign, 0x9C, absA, rounding_mode );
+    }
+
+    mark_f_state_dirty();
 
-      

arch/inst/F/fcvt.w.s.yaml

@@ -51,4 +51,30 @@ fcvt.w.s:
     vu: always
   data_independent_timing: true
   operation(): |
-      
+      check_f_ok();
+
+      Bits<32> sp_value = f[fs1][31:0];
+
+      Bits<1> sign = sp_value[31];
+      Bits<8> exp = sp_value[30:23];
+      Bits<23> sig = sp_value[22:0];
+
+      RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
+
+      if ( (exp == 0xff) && (sig != 0)) {
+        sign = 0;
+        set_fp_flag(FpFlag::NV);
+        X[rd] = SP_CANONICAL_NAN;
+      } else {
+        if (exp != 0) {
+          sig = sig | 0x00800000;
+        }
+        Bits<64> sig64 = sig << 32;
+        Bits<16> shift_dist = 0xAA - exp;
+        if (0 < shift_dist) {
+          sig64 = softfloat_shiftRightJam64(sig64, shift_dist );
+        }
+        X[rd] = softfloat_roundToI32( sign, sig64, rounding_mode );
+      }
+
+

arch/inst/F/feq.s.yaml

@@ -27,3 +27,19 @@ feq.s:
     vu: always
   data_independent_timing: true
   operation(): |
+    check_f_ok();
+
+    Bits<32> sp_value_a = f[fs1][31:0];
+    Bits<32> sp_value_b = f[fs1][31:0];
+
+    if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
+      if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
+        set_fp_flag(FpFlag::NV);
+      }
+      X[rd] = 0;
+    } else {
+      X[rd] = (
+        (sp_value_a == sp_value_b)
+        || ((sp_value_a | sp_value_b)[30:0] == 0) # pos 0 is equal to neg zero
+      ) ? 1 : 0;
+    }

arch/inst/F/fle.s.yaml

@@ -28,3 +28,19 @@ fle.s:
     vu: always
   data_independent_timing: true
   operation(): |
+    check_f_ok();
+
+    Bits<32> sp_value_a = f[fs1][31:0];
+    Bits<32> sp_value_b = f[fs1][31:0];
+
+    if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
+      if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
+        set_fp_flag(FpFlag::NV);
+      }
+      X[rd] = 0;
+    } else {
+      X[rd] = (
+        (sp_value_a == sp_value_b)
+        || ((sp_value_a | sp_value_b)[30:0] == 0) # pos 0 is equal to neg zero
+      ) ? 1 : 0;
+    }

arch/inst/F/flt.s.yaml

@@ -26,5 +26,23 @@ flt.s:
     vu: always
   data_independent_timing: true
   operation(): |
+    check_f_ok();
+
+    Bits<32> sp_value_a = f[fs1][31:0];
+    Bits<32> sp_value_b = f[fs1][31:0];
+
+    if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
+      set_fp_flag(FpFlag::NV);
+      X[rd] = 0;
+    } else {
+      Boolean sign_a = sp_value_a[31] == 1;
+      Boolean sign_b = sp_value_b[31] == 1;
+
+      Boolean a_lt_b = 
+        (sign_a != sign_b)
+          ? (sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0)) # opposite sign, a is negative. a is less than b as long as both are not zero
+          : ((sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b)));
+      X[rd] = a_lt_b ? 1 : 0;
+    }
 
 

arch/inst/F/flw.yaml

@@ -25,3 +25,16 @@ flw:
     vu: always
   data_independent_timing: true
   operation(): |
+    check_f_ok();
+
+    XReg virtual_address = X[rs1] + $signed(imm);
+
+    Bits<32> sp_value = read_memory<32>(virtual_address);
+
+    if (implemented?(ExtensionName::D)) {
+      f[fd] = nan_box(sp_value);
+    } else {
+      f[fd] = sp_value;
+    }
+
+    mark_f_state_dirty();

arch/inst/F/fmv.w.x.yaml

@@ -23,4 +23,14 @@ fmv.w.x:
     vu: always
   data_independent_timing: true
   operation(): |
+    check_f_ok();
 
+    Bits<32> sp_value = X[rs1][31:0];
+
+    if (implemented?(ExtensionName::D)) {
+      f[fd] = nan_box(sp_value);
+    } else {
+      f[fd] = sp_value;
+    }
+
+    mark_f_state_dirty();

arch/inst/F/fsgnj.s.yaml

@@ -25,3 +25,14 @@ fsgnj.s:
     vu: always
   data_independent_timing: true
   operation(): |
+    check_f_ok();
+
+    Bits<32> sp_value = {f[fs2][31], f[fs1][30:0]};
+
+    if (implemented?(ExtensionName::D)) {
+      f[fd] = nan_box(sp_value);
+    } else {
+      f[fd] = sp_value;
+    }
+
+    mark_f_state_dirty();

arch/inst/F/fsgnjn.s.yaml

@@ -24,3 +24,14 @@ fsgnjn.s:
     vu: always
   data_independent_timing: true
   operation(): |
+    check_f_ok();
+
+    Bits<32> sp_value = {~f[fs2][31], f[fs1][30:0]};
+
+    if (implemented?(ExtensionName::D)) {
+      f[fd] = nan_box(sp_value);
+    } else {
+      f[fd] = sp_value;
+    }
+
+    mark_f_state_dirty();