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| 1 | +# yaml-language-server: $schema=../../schemas/ext_schema.json |
| 2 | + |
| 3 | +$schema: "ext_schema.json#" |
| 4 | +kind: extension |
| 5 | +name: Zcmp |
| 6 | +long_name: 16-bit Push/Pop instructions |
| 7 | +description: | |
| 8 | + The Zcmp extension is a set of instructions which may be executed as a series of existing 32-bit RISC-V instructions. |
| 9 | +
|
| 10 | + This extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with <<Zcd>>, |
| 11 | + which is included when C and D extensions are both present. |
| 12 | +
|
| 13 | + NOTE: Zcmp is primarily targeted at embedded class CPUs due to implementation complexity. Additionally, it is not compatible with architecture class profiles. |
| 14 | +
|
| 15 | + The Zcmp extension depends on the <<Zca>> extension. |
| 16 | +
|
| 17 | + The PUSH/POP assembly syntax uses several variables, the meaning of which are: |
| 18 | +
|
| 19 | + * _reg_list_ is a list containing 1 to 13 registers (ra and 0 to 12 s registers) |
| 20 | + ** valid values: {ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2}, ..., {ra, s0-s8}, {ra, s0-s9}, {ra, s0-s11} |
| 21 | + ** note that {ra, s0-s10} is _not_ valid, giving 12 lists not 13 for better encoding |
| 22 | + * _stack_adj_ is the total size of the stack frame. |
| 23 | + ** valid values vary with register list length and the specific encoding, see the instruction pages for details. |
| 24 | +
|
| 25 | + [%header,cols="^1,^1,4,8"] |
| 26 | + |=== |
| 27 | + |RV32 |
| 28 | + |RV64 |
| 29 | + |Mnemonic |
| 30 | + |Instruction |
| 31 | +
|
| 32 | + |yes |
| 33 | + |yes |
| 34 | + |cm.push _{reg_list}, -stack_adj_ |
| 35 | + |<<#insns-cm_push>> |
| 36 | +
|
| 37 | + |yes |
| 38 | + |yes |
| 39 | + |cm.pop _{reg_list}, stack_adj_ |
| 40 | + |<<#insns-cm_pop>> |
| 41 | +
|
| 42 | + |yes |
| 43 | + |yes |
| 44 | + |cm.popret _{reg_list}, stack_adj_ |
| 45 | + |<<#insns-cm_popret>> |
| 46 | +
|
| 47 | + |yes |
| 48 | + |yes |
| 49 | + |cm.popretz _{reg_list}, stack_adj_ |
| 50 | + |<<#insns-cm_popretz>> |
| 51 | +
|
| 52 | + |yes |
| 53 | + |yes |
| 54 | + |cm.mva01s _rs1', rs2'_ |
| 55 | + |<<#insns-cm_mva01s>> |
| 56 | +
|
| 57 | + |yes |
| 58 | + |yes |
| 59 | + |cm.mvsa01 _r1s', r2s'_ |
| 60 | + |<<#insns-cm_mvsa01>> |
| 61 | +
|
| 62 | + |=== |
| 63 | +
|
| 64 | +type: unprivileged |
| 65 | +company: |
| 66 | + name: RISC-V International |
| 67 | + url: https://riscv.org |
| 68 | +versions: |
| 69 | + - version: "1.0.0" |
| 70 | + state: ratified |
| 71 | + ratification_date: 2023-04 |
| 72 | + repositories: |
| 73 | + - url: https://github.com/riscv/riscv-code-size-reduction |
| 74 | + branch: main |
| 75 | + contributors: |
| 76 | + - name: Tariq Kurd |
| 77 | + - name: Ibrahim Abu Kharmeh |
| 78 | + - name: Torbjørn Viem Ness |
| 79 | + - name: Matteo Perotti |
| 80 | + - name: Nidal Faour |
| 81 | + - name: Bill Traynor |
| 82 | + - name: Rafael Sene |
| 83 | + - name: Xinlong Wu |
| 84 | + - name: sinan |
| 85 | + - name: Jeremy Bennett |
| 86 | + - name: Heda Chen |
| 87 | + - name: Alasdair Armstrong |
| 88 | + - name: Graeme Smecher |
| 89 | + - name: Nicolas Brunie |
| 90 | + - name: Jiawei |
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