Merge pull request #241 from riscv-software-src/58-reduce-duplicate-code-between-profiles-and-crds

Created common base class called "Portfolio" that both Profiles and CRDs use.

Author: james-ball-qualcomm

.github/workflows/pages.yml

@@ -58,7 +58,7 @@ jobs:
     - name: Copy cfg html
       run: cp -R gen/cfg_html_doc/generic_rv64/html _site/example_cfg
     - name: Create RVA Family PDF Spec
-      run: ./do gen:profile_pdf[rva]
+      run: ./do gen:profile[rva]
     - name: Copy RVA Family PDF
       run: cp gen/profile_doc/pdf/rva.pdf _site/pdfs/rva.pdf
     - name: Create MC-1 PDF Spec

.gitignore

@@ -10,6 +10,7 @@
 diag-ditaa-*
 arch/manual/isa/**/riscv-isa-manual
 gen
+gen_expected
 node_modules
 _site
 images

Rakefile

@@ -289,7 +289,8 @@ task :regress do
   Rake::Task["gen:html"].invoke("generic_rv64")
   Rake::Task["gen:crd_pdf"].invoke("MockCRD-1")
   Rake::Task["gen:crd_pdf"].invoke("MC-1")
-  Rake::Task["gen:profile_pdf"].invoke("rva")
+  Rake::Task["gen:profile"].invoke("MockProfileFamily")
+  Rake::Task["gen:profile"].invoke("rva")
 
   puts
   puts "Regression test PASSED"

arch/crd/MC-1.yaml

@@ -8,6 +8,59 @@ MC-1:
   # semantic version within the CRD family
   version: "1.0"
 
+  revision_history:
+  - revision: "0.7"
+    date: 2024-07-29
+    changes:
+    - First version after moving non-microcontroller content in this document to a new document
+      called “RISC-V CRDs (Certification Requirement Documents)”
+    - Change MC-1 Unpriv ISA spec from
+      “https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
+      2016” to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
+      former isn't ratified by the latter is the oldest ratified version.
+    - Added requirements for WFI instruction
+    - Added requirements related to msip memory-mapped register
+  - revision: "0.6"
+    date: 2024-07-11
+    changes:
+    - Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
+    - Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
+    - Added a table showing the mapping from MC version to ISA manuals.
+    - Reluctantly made interrupts OUT OF SCOPE for MC-1 since only the CLINT interrupt controller
+      was ratified at that time and isn’t anticipated to be the interrupt controller used by MC-1 implementations.
+    - Clarified MANDATORY behaviors for mie and mip CSRs
+    - Removed canonical discovery recipe because the OPT-* options directly inform the certification
+      tests and certification reference model of the status of the various options. Also, canonical
+      discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
+      potentially illegal values to CSR fields.
+    - Added more options for interrupts
+    - Moved non-microcontroller content in this document to a new document called “RISC-V Certification Plans”
+  - revision: "0.5"
+    date: 2024-06-03
+    changes:
+    - Renamed to “RISC-V Microcontroller Certification Plan” based on Jason’s recommendation
+    - Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
+      these are mandatory in M-mode v1.13 (probably older versions too, haven’t looked yet).
+    - Added table showing mapping of MC versions to associated RISC-V specifications
+  - revision: "0.4"
+    date: 2024-06-03
+    changes:
+    - Added M-mode instruction requirements
+    - Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
+    - Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
+  - revision: "0.3"
+    date: 2024-05-25
+    changes:
+    - Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
+  - revision: "0.2"
+    date: 2024-05-20
+    changes:
+    - Very early draft
+  - revision: "0.1"
+    date: 2024-05-16
+    changes:
+    - Initial version
+
   # XLEN used by rakefile
   base: 32
 

arch/crd/MockCRD-1.yaml

@@ -12,6 +12,16 @@ MockCRD-1:
   # semantic version within the CRD family
   version: "1.0"
 
+  revision_history:
+  - revision: "0.1"
+    date: 2024-10-04
+    changes:
+    - Created to test CRDs
+  - revision: "0.2"
+    date: 2024-10-05
+    changes:
+    - Also created to test CRDs
+
   description: |
     Mock CRD description:
 

arch/crd_family/MockCRDFamily.yaml

@@ -1,15 +1,6 @@
 MockCRDFamily:
   name: MockCRDFamily
   long_name: Mock CRD Family Long Name
-  revision_history:
-  - version: "0.1"
-    date: 2024-10-04
-    changes:
-    - Created to test CRDs
-  - version: "0.2"
-    date: 2024-10-05
-    changes:
-    - Also created to test CRDs
 
   introduction: |
     Here's the Mock CRD Family's introduction.
@@ -18,4 +9,6 @@ MockCRDFamily:
     Here's the Mock CRD Family's naming scheme.
 
   mandatory_priv_modes:
-  - M
+  - M
+
+  description: Here's the Mock CRD Family's description.

arch/profile/MockProfile-1.yaml

@@ -0,0 +1,28 @@
+MockProfile-1:
+  family: MockProfileFamily
+  description: This is the Mock Profile description.
+  marketing_name: MockProfile-1 Marketing Name
+  mode: S
+  version: "1.0"
+  contributors:
+  - name: Krste Asanovic
+    email: [email protected]
+    company: SiFive
+  extensions:
+  - name: S
+    presence: mandatory
+    version: "= 1.11"
+  - name: Zifencei
+    presence: mandatory
+    version: "= 2.0"
+    note: |
+      Zifencei is mandated as it is the only standard way to support
+      instruction-cache coherence in RVA20 application processors.  A new
+      instruction-cache coherence mechanism is under development which might
+      be added as an option in the future.
+  - name: Zihpm
+    presence: optional
+    version: "= 2.0"
+  - name: Sv48
+    presence: optional
+    version: "= 1.11"

arch/profile/rva20s64.yaml

@@ -7,7 +7,6 @@ rva20s64:
     processors.  RVA20S64 is based on privileged architecture version
     1.11.
   marketing_name: RVA20S64
-  inherits: rva20u64
   mode: S
   version: "1.0"
   contributors:

arch/profile/rva20u64.yaml

@@ -102,16 +102,15 @@ rva20u64:
     version: "= 2.0"
     note: |
       The number of counters is platform-specific.
-  - name: Q
-    presence: excluded
+  extra_notes:
+  - location: optional
     note: |
       The rationale to not make Q an optional extension is that
       quad-precision floating-point is unlikely to be implemented in
       hardware, and so we do not require or expect A-profile software to
       expend effort optimizing use of Q instructions in case they are
       present.
-  - name: Zifencei
-    presence: excluded
+  - location: optional
     note: |
       Zifencei is not classed as a supported option in the user-mode
       profile because it is not sufficient by itself to produce the desired
@@ -123,7 +122,8 @@ rva20u64:
       instruction-cache coherence mechanisms can be used behind the OS
       abstraction.  A separate extension is being developed for more general
       and efficient instruction cache coherence.
-
+  - location: optional
+    note: |
       The execution environment must provide a means to synchronize writes to
       instruction memory with instruction fetches, the implementation of which
       likely relies on the Zifencei extension.

arch/profile/rva22s64.yaml

@@ -6,7 +6,6 @@ rva22s64:
     supervisor-mode execution environment in 64-bit applications
     processors.  RVA22S64 is based on privileged architecture version
     1.12.
-  inherits: rva22u64
   version: "2.0"
   mode: S
   marketing_name: RVA22S64