Merge branch 'main' into 181-move-priv-modes-present-from-crd-family-to-crd

Author: james-ball-qualcomm

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,25 @@
+---
+name: Bug report
+about: Report a bug in one or more tools
+title: ''
+labels: bug
+assignees: ''
+
+---
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behavior:
+1. On branch B,
+1. Run '...'
+
+**Text output/Error Messages**
+If any
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
+
+**Additional context**
+Add any other context about the problem here.

.github/ISSUE_TEMPLATE/data-error.md

@@ -0,0 +1,14 @@
+---
+name: Data Error
+about: Report a data error in the database
+title: ''
+labels: data error
+assignees: ''
+
+---
+
+**Current value and location**
+Where is this data?
+
+**Expected value**
+What do you think the value(s) should be?

.github/ISSUE_TEMPLATE/feature_request.md

@@ -0,0 +1,20 @@
+---
+name: Feature request
+about: Suggest an idea for this project
+title: ''
+labels: enhancement
+assignees: ''
+
+---
+
+**Is your feature request related to a problem? Please describe.**
+A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
+
+**Describe the solution you'd like**
+A clear and concise description of what you want to happen.
+
+**Describe alternatives you've considered**
+A clear and concise description of any alternative solutions or features you've considered.
+
+**Additional context**
+Add any other context or screenshots about the feature request here.

arch/csr/mie.yaml

@@ -156,6 +156,7 @@ mie:
 
         Alias of `sie.SSIE` when `mideleg.SSI` is set. Otherwise, `sie.SSIE` is read-only 0.
       type: RW
+      definedBy: S
       reset_value: 0
     VSSIE:
       location: 2
@@ -188,6 +189,7 @@ mie:
 
         Alias of `sip.STIE` when `mideleg.STI` is set. Otherwise, `sip.STIE` is read-only 0.
       type: RW
+      definedBy: S
       reset_value: 0
     VSTIE:
       location: 6
@@ -220,6 +222,7 @@ mie:
 
         Alias of `sie.SEIE` when `mideleg.SEI` is set. Otherwise, `sie.SEIE` is read-only 0.
       type: RW
+      definedBy: S
       reset_value: 0
     VSEIE:
       location: 10

arch/csr/misa.yaml

@@ -23,8 +23,8 @@ misa:
         Writing 0 to this field will cause all atomic instructions to raise an `IllegalInstruction` exception.
       type(): |
         return (implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::A) ? 1 : 0;
+      definedBy: A
+      reset_value: 1
     B:
       location: 1
       description: |
@@ -34,8 +34,8 @@ misa:
         Writing 0 to this field will cause all bitmanip instructions to raise an `IllegalInstruction` exception.
       type(): |
         return (implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::B) ? 1 : 0;
+      definedBy: B
+      reset_value: 1
     C:
       location: 2
       description: |
@@ -46,8 +46,8 @@ misa:
         Additionally, IALIGN becomes 32.
       type(): |
         return (implemented?(ExtensionName::C) && MUTABLE_MISA_C) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::C) ? 1 : 0;
+      definedBy: C
+      reset_value: 1
     D:
       location: 3
       description: |
@@ -61,8 +61,8 @@ misa:
         --
       type(): |
         return (implemented?(ExtensionName::D) && MUTABLE_MISA_D) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::D) ? 1 : 0;
+      definedBy: D
+      reset_value: 1
     F:
       location: 5
       description: |
@@ -76,8 +76,8 @@ misa:
         --
       type(): |
         return (implemented?(ExtensionName::F) && MUTABLE_MISA_F) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::F) ? 1 : 0;
+      definedBy: F
+      reset_value: 1
       sw_write(csr_value): |
         if (csr_value.F == 0 && csr_value.D == 1) {
           return UNDEFINED_LEGAL_DETERMINISTIC;
@@ -115,13 +115,14 @@ misa:
         Writing 0 to this field will cause all attempts to enter VS- or VU- mode, execute a hypervisor instruction, or access a hypervisor CSR to raise an `IllegalInstruction` fault.
       type(): |
         return (implemented?(ExtensionName::H) && MUTABLE_MISA_H) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::H) ? 1 : 0;
+      definedBy: H
+      reset_value: 1
     I:
       location: 8
       description: |
         Indicates support for the `I` (base) extension.
       type: RO
+      definedBy: I
       reset_value: 1
     M:
       location: 13
@@ -132,8 +133,8 @@ misa:
         Writing 0 to this field will cause all attempts to execute an integer multiply or divide instruction to raise an `IllegalInstruction` exception.
       type(): |
         return (implemented?(ExtensionName::M) && MUTABLE_MISA_M) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::M) ? 1 : 0;
+      definedBy: M
+      reset_value: 1
     S:
       location: 19
       description: |
@@ -143,8 +144,8 @@ misa:
         Writing 0 to this field will cause all attempts to enter S-mode or access S-mode state to raise an exception.
       type(): |
         return (implemented?(ExtensionName::S) && MUTABLE_MISA_S) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::S) ? 1 : 0;
+      definedBy: S
+      reset_value: 1
     U:
       location: 21
       description: |
@@ -154,19 +155,18 @@ misa:
         Writing 0 to this field will cause all attempts to enter U-mode to raise an exception.
       type(): |
         return (implemented?(ExtensionName::U) && MUTABLE_MISA_U) ? CsrFieldType::RW : CsrFieldType::RO;
-      reset_value(): |
-        return implemented?(ExtensionName::U) ? 1 : 0;
+      definedBy: U
+      reset_value: 1
     V:
       location: 22
       description: |
         Indicates support for the `V` (vector) extension.
 
-        [when,"MUTABLE_MISA_S == true"]
+        [when,"MUTABLE_MISA_V == true"]
         Writing 0 to this field will cause all attempts to execute a vector instruction to raise an `IllegalInstruction` trap.
       type: RO
-      reset_value: 0 # TODO
-      # reset_value(): |
-      #   return implemented?(ExtensionName::V) ? 1 : 0;
+      definedBy: V
+      reset_value: 1
   sw_read(): |
     return (
       (CSR[misa].MXL << 62) |

arch/prose/idl.adoc

@@ -144,7 +144,7 @@ There are several aliases of Bits<N> available, as shown below.
 |===
 | Alias | Type
 
-| `XReg`  | `Bits<XLEN>`, where XLEN is configuratin-dependent
+| `XReg`  | `Bits<XLEN>`, where XLEN is configuration-dependent
 | `U64`   | `Bits<64>`
 | `U32`   | `Bits<32>`
 |===
@@ -249,7 +249,7 @@ Arrays are declared by appending the size of the array in brackets after the var
 .Array declarations
 [source,idl]
 ----
-Bitx<32> array_of_words[10];      # array of ten words
+Bits<32> array_of_words[10];      # array of ten words
 Boolean  array_of_bools[12];      # array of twelve booleans
 Bits<32> matrix_of_words[32][32]; # array of arrays of 32 words
 ----
@@ -264,7 +264,7 @@ array_of_bools[3]      # Boolean type; the third word in array_of_bools
 matrix_of_words[3][4]  # Bits<32> type; the fourth word in the third array of matrix_of_words
 ----
 
-Arrays cannot be casted to Bits<N> type, so the storage order is irrelant and unspecified.
+Arrays cannot be casted to Bits<N> type, so the storage order is irrelevant and unspecified.
 
 ==== Tuples
 
@@ -309,7 +309,7 @@ Literals may contain any number of underscores after the initial digit for clari
 4'sb1101      # -3 decimal, signed, 4-bit wide
 -4'sb1101     #  3 decimal, signed, 4-bit wide
 
-32'h80000000  # 0x8000000, unsigned, 32-bit wide
+32'h80000000  # 0x80000000, unsigned, 32-bit wide
 32'h8000_0000 # same as above (underscores ignored)
 
 8'13          # 13 decimal, 8-bit wide (default radix is 10)
@@ -340,7 +340,7 @@ Literals may contain any number of underscores after the initial digit for clari
 0x0fff      # 4095 decimal, unsigned 12-bit wide (leading zeros have no impact)
 0           # 0 decimal, unsigned, 1-bit wide (0 is specially defined to be 1-bit wide)
 
-0x80000000  # 0x8000000, unsigned, 32-bit wide
+0x80000000  # 0x80000000, unsigned, 32-bit wide
 0x8000_0000 # same as above (underscores ignored)
 
 # negative literals
@@ -360,7 +360,7 @@ Array literals are composed of a list of comma-separated values in brackets, sim
 .Array literals
 [source,idl]
 ----
-Bitx<32> array_of_words[10] = [0,1,2,3,4,5,6,7,8,9];
+Bits<32> array_of_words[10] = [0,1,2,3,4,5,6,7,8,9];
 Boolean  array_of_bools[12] =
   [
     true,true,true,true,true,true,
@@ -509,7 +509,7 @@ Variables may be optionally initialized when they are declared using the assignm
 [source,idl]
 ----
 Boolean condition;              # declare condition, initialized to false
-XReg    address = 0x8000_0000;  # declare address, initialized to 0x800000000
+XReg    address = 0x8000_0000;  # declare address, initialized to 0x80000000
 Bits<8> pmpCfg0;                # declare pmpCfg0, initialized to 8'd0
 Bits<8> pmp_cfg_0;              # declare pmp_cfg_0, initialized to 8'd0
 Bits<8> ary[2];                 # declare ary, initialized to [8'd0, 8'd0]
@@ -550,8 +550,8 @@ Note that many global constants, such are configuration parameters, are implicit
 [source,idl]
 ----
 Boolean I_LIKE_CHEESE = true;   # declare I_LIKE_CHEESE, initialized to true
-XReg    Address = 0x8000_0000;  # declare Address, initialized to 0x800000000
-XReg    AddressAlias = Address; # declare AddressAlias, initialized to 0x800000000
+XReg    Address = 0x8000_0000;  # declare Address, initialized to 0x80000000
+XReg    AddressAlias = Address; # declare AddressAlias, initialized to 0x80000000
 
 # Bits<8> pmpCfg;  # constant names must start with a lowercase letter. pmpCfg would be a variable
 
@@ -592,7 +592,7 @@ Bitfields can be converted to a `Bits<N>` type, where N is the width of the bitf
 
 == Casting
 
-There are two explicit cast operators in IDL: `$isgned` and `$bits`.
+There are two explicit cast operators in IDL: `$isigned` and `$bits`.
 
 Unsigned Bits<N> values may be cast to signed values using the `$signed` cast operator.
 

backends/crd_doc/templates/crd.adoc.erb

@@ -544,7 +544,7 @@ h| Privilege Mode | <%= csr.priv_mode %>
 .<%= csr.name %> format
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-<%= JSON.dump csr.wavedrom_desc(arch_def, csr.base.nil? ? 32 : csr.base, optional_type: 3) %>
+<%= JSON.dump csr.wavedrom_desc(arch_def, csr.base.nil? ? 32 : csr.base, optional_type: 2) %>
 ....
 <% else -%>
 <%# CSR has a dynamic length, or a field has a dynamic location,
@@ -554,13 +554,13 @@ This CSR format changes dynamically with XLEN.
 .<%= csr.name %> Format when <%= csr.length_cond32 %>
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-<%= JSON.dump csr.wavedrom_desc(arch_def, 32, optional_type: 3) %>
+<%= JSON.dump csr.wavedrom_desc(arch_def, 32, optional_type: 2) %>
 ....
 
 .<%= csr.name %> Format when <%= csr.length_cond64 %>
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-<%= JSON.dump csr.wavedrom_desc(arch_def, 64, optional_type: 3) %>
+<%= JSON.dump csr.wavedrom_desc(arch_def, 64, optional_type: 2) %>
 ....
 
 

lib/arch_obj_models/csr.rb

@@ -512,7 +512,7 @@ def pruned_sw_read_ast(arch_def)
   # @param exclude_unimplemented [Boolean] If true, do not create include unimplemented fields in the figure
   # @param optional_type [Integer] Wavedrom type (Fill color) for fields that are optional (not mandatory) in a partially-specified arch_def
   # @return [Hash] A representation of the WaveDrom drawing for the CSR (should be turned into JSON for wavedrom)
-  def wavedrom_desc(arch_def, effective_xlen, exclude_unimplemented: false, optional_type: 2)
+  def wavedrom_desc(arch_def, effective_xlen, exclude_unimplemented: false, optional_type: 3)
     desc = {
       "reg" => []
     }
@@ -536,9 +536,10 @@ def wavedrom_desc(arch_def, effective_xlen, exclude_unimplemented: false, option
         desc["reg"] << { "bits" => n, type: 1 }
       end
       if arch_def.partially_configured? && field.optional_in_cfg?(arch_def)
+        puts "#{name}.#{field.name} is OPTIONAL"
         desc["reg"] << { "bits" => field.location(arch_def, effective_xlen).size, "name" => field.name, type: optional_type }
       else
-        desc["reg"] << { "bits" => field.location(arch_def, effective_xlen).size, "name" => field.name, type: 2 }
+        desc["reg"] << { "bits" => field.location(arch_def, effective_xlen).size, "name" => field.name, type: 3 }
       end
       last_idx = field.location(arch_def, effective_xlen).max
     end
@@ -570,7 +571,7 @@ def optional_in_cfg?(arch_def)
     raise "optional_in_cfg? should only be used by a partially-specified arch def" unless arch_def.partially_configured?
 
     exists_in_cfg?(arch_def) &&
-      arch_def.mandatory_extensions.none? do |ext_req|
+      arch_def.mandatory_extensions.all? do |ext_req|
         ext_req.satisfying_versions(arch_def).none? { |ext_ver| defined_by?(ext_ver) }
       end
   end

lib/arch_obj_models/csr_field.rb

@@ -52,7 +52,7 @@ def optional_in_cfg?(arch_def)
     exists_in_cfg?(arch_def) &&
       (
         parent.optional_in_cfg?(arch_def) ||
-        (data["definedBy"].nil? || arch_def.mandatory_extensions.none? do |ext_req|
+        (data["definedBy"].nil? || arch_def.mandatory_extensions.all? do |ext_req|
           ext_req.satisfying_versions(arch_def).none? { |ext_ver| defined_by?(ext_ver) }
         end)
       )

lib/arch_obj_models/extension.rb

@@ -316,6 +316,10 @@ def params(arch_def)
     ext(arch_def).params.select { |p| p.defined_in_extension_version?(@version) }
   end
 
+  def to_s
+    "#{name}@#{version}"
+  end
+
   # @overload ==(other)
   #   @param other [String] An extension name
   #   @return [Boolean] whether or not this ExtensionVersion is named 'other'