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Merged F extension instructions. Some fields are not populated
Signed-off-by: Afonso Oliveira <[email protected]>
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‎arch/inst/F/fabs.s.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fabs.s:
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long_name: No synopsis available.
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description: |
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No description available.
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definedBy: F
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assembly: xd, xs1, xs2=xs1
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encoding:
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match: 0010000----------010-----1010011
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variables:
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- name: rs2=rs1
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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‎arch/inst/F/fadd.s.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fadd.s:
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long_name: No synopsis available.
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description: |
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No description available.
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definedBy: F
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assembly: xd, xs1, xs2, rm
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encoding:
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match: 0000000------------------1010011
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variables:
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- name: rs2
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location: 24-20
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- name: rs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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‎arch/inst/F/fclass.s.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fclass.s:
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long_name: Single-precision floating-point classify.
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description: |
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The `fclass.s` instruction examines the value in floating-point register
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_fs1_ and writes to integer register _rd_ a 10-bit mask that indicates
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the class of the floating-point number.
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The format of the mask is described in the table below.
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The corresponding bit in _rd_ will be set if the property is true and
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clear otherwise.
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All other bits in _rd_ are cleared.
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Note that exactly one bit in rd will be set.
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`fclass.s` does not set the floating-point exception flags.
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.Format of result of `fclass` instruction.
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[%autowidth,float="center",align="center",cols="^,<",options="header",]
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|===
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|_rd_ bit |Meaning
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|0 |_rs1_ is latexmath:[$-\infty$].
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|1 |_rs1_ is a negative normal number.
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|2 |_rs1_ is a negative subnormal number.
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|3 |_rs1_ is latexmath:[$-0$].
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|4 |_rs1_ is latexmath:[$+0$].
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|5 |_rs1_ is a positive subnormal number.
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|6 |_rs1_ is a positive normal number.
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|7 |_rs1_ is latexmath:[$+\infty$].
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|8 |_rs1_ is a signaling NaN.
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|9 |_rs1_ is a quiet NaN.
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|===
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definedBy: F
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assembly: xd, fs1
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encoding:
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match: 111000000000-----001-----1010011
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variables:
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- name: fs1
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location: 19-15
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: false
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operation(): |
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‎arch/inst/F/fcvt.l.s.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fcvt.l.s:
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long_name: No synopsis available.
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description: |
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No description available.
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definedBy: F
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base: 64
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assembly: xd, xs1, rm
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encoding:
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match: 110000000010-------------1010011
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variables:
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- name: rs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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‎arch/inst/F/fcvt.lu.s.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fcvt.lu.s:
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long_name: No synopsis available.
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description: |
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No description available.
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definedBy: F
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base: 64
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assembly: xd, xs1, rm
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encoding:
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match: 110000000011-------------1010011
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variables:
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- name: rs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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‎arch/inst/F/fcvt.s.l.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fcvt.s.l:
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long_name: No synopsis available.
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description: |
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No description available.
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definedBy: F
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base: 64
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assembly: xd, xs1, rm
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encoding:
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match: 110100000010-------------1010011
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variables:
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- name: rs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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‎arch/inst/F/fcvt.s.lu.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fcvt.s.lu:
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long_name: No synopsis available.
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description: |
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No description available.
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definedBy: F
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base: 64
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assembly: xd, xs1, rm
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encoding:
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match: 110100000011-------------1010011
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variables:
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- name: rs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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‎arch/inst/F/fcvt.s.w.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fcvt.s.w:
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long_name: Convert signed 32-bit integer to single-precision float
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description: |
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Converts a 32-bit signed integer in integer register _rs1_ into a floating-point number in
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floating-point register _fd_.
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All floating-point to integer and integer to floating-point conversion instructions round
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according to the _rm_ field.
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A floating-point register can be initialized to floating-point positive zero using
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`fcvt.s.w rd, x0`, which will never set any exception flags.
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All floating-point conversion instructions set the Inexact exception flag if the rounded
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result differs from the operand value and the Invalid exception flag is not set.
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definedBy: F
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assembly: fd, xs1
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encoding:
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match: 110100000000-------------1010011
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variables:
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- name: rs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: false
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operation(): |
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‎arch/inst/F/fcvt.s.wu.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fcvt.s.wu:
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long_name: No synopsis available.
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description: |
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No description available.
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definedBy: F
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assembly: xd, xs1, rm
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encoding:
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match: 110100000001-------------1010011
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variables:
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- name: rs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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‎arch/inst/F/fcvt.w.s.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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fcvt.w.s:
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long_name: Convert single-precision float to integer word to signed 32-bit integer.
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description: |
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Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates
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integer register _rd_.
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For XLEN &gt;32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width.
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If the rounded result is not representable as a 32-bit signed integer, it is clipped to the
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nearest value and the invalid flag is set.
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The range of valid inputs and behavior for invalid inputs are:
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[separator="!"]
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!===
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! ! Value
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h! Minimum valid input (after rounding) ! `-2^31`
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h! Maximum valid input (after rounding) ! `2^31 - 1`
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h! Output for out-of-range negative input ! `-2^31`
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h! Output for `-&infin;` ! `-2^31`
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h! Output for out-of-range positive input ! `2^31 - 1`
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h! Output for `+&infin;` for `NaN` ! `2^31 - 1`
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!===
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All floating-point to integer and integer to floating-point conversion instructions round
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according to the _rm_ field.
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A floating-point register can be initialized to floating-point positive zero using
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`fcvt.s.w rd, x0`, which will never set any exception flags.
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All floating-point conversion instructions set the Inexact exception flag if the rounded
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result differs from the operand value and the Invalid exception flag is not set.
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definedBy: F
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assembly: xd, fs1
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encoding:
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match: 110000000000-------------1010011
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variables:
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- name: fs1
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location: 19-15
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- name: rm
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location: 14-12
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- name: rd
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location: 11-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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data_independent_timing: true
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operation(): |
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