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dhower-qcdhower-qc
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Merge branch 'main' into nightly-fix
2 parents d34fd02 + f716423 commit 2471697

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+220
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lines changed

‎.devcontainer/Dockerfile‎

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@@ -6,27 +6,35 @@ WORKDIR /workspace
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RUN export DEBIAN_FRONTEND=noninteractive
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RUN apt-get update
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RUN apt-get install -y --no-install-recommends git \
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gh \
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less \
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python3 \
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python3.12-venv \
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python3-pip \
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build-essential \
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ruby \
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ruby-dev \
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bundler \
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nodejs \
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npm \
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ditaa \
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libyaml-dev \
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cmake \
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g++ \
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clang-format \
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clang-tidy \
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libelf-dev \
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gcc-riscv64-unknown-elf \
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shellcheck
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# please keep pkgs sorted
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RUN apt-get install -y --no-install-recommends \
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build-essential \
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bundler \
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clang-format \
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clang-tidy \
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cmake \
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ditaa \
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g++ \
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gcc-riscv64-linux-gnu \
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gcc-riscv64-unknown-elf \
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gdb \
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gh \
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git \
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less \
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libc6-dev-riscv64-cross \
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libelf-dev \
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libgmp-dev \
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libyaml-dev \
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nodejs \
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npm \
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python3 \
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python3-pip \
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python3.12-venv \
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ruby \
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ruby-dev \
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shellcheck
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RUN apt-get clean autoclean
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RUN apt-get autoremove -y
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RUN rm -rf /var/lib/{apt,dpkg,cache,log}/*

‎arch_overlay/qc_iu/ext/Xqci.yaml‎

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@@ -268,6 +268,50 @@ versions:
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requires:
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name: Zca
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version: ">= 1.0.0"
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- version: "0.9.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
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- Fix IDL code sign extension logic for qc.ext and qc.extd instructions
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- Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdr and qc.extdur instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
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- Fix IDL code sign extension logic for qc.lieq instruction
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- Fix wrong mantissa bit selection in qc.norm, qc.normu and qc.normeu instructions
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- Fix wrong exponent calculation in qc.normeu instruction
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- Fix IDL code and description of qc.setwm instruction to state that number of words written 0..31.
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- Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions
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implies:
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- { name: Xqcia, version: "0.6.0" }
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- { name: Xqciac, version: "0.3.0" }
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- { name: Xqcibi, version: "0.2.0" }
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- { name: Xqcibm, version: "0.7.0" }
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- { name: Xqcicli, version: "0.3.0" }
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- { name: Xqcicm, version: "0.2.0" }
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- { name: Xqcics, version: "0.2.0" }
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- { name: Xqcicsr, version: "0.3.0" }
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- { name: Xqciint, version: "0.6.0" }
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- { name: Xqciio, version: "0.1.0" }
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- { name: Xqcilb, version: "0.2.0" }
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- { name: Xqcili, version: "0.2.0" }
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- { name: Xqcilia, version: "0.2.0" }
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- { name: Xqcilo, version: "0.3.0" }
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- { name: Xqcilsm, version: "0.5.0" }
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- { name: Xqcisim, version: "0.2.0" }
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- { name: Xqcisls, version: "0.2.0" }
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- { name: Xqcisync, version: "0.2.0" }
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requires:
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name: Zca
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version: ">= 1.0.0"
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description: |
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The Xqci extension includes a set of instructions that improve RISC-V code density and
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performance in microontrollers. It fills several gaps:

‎arch_overlay/qc_iu/ext/Xqcia.yaml‎

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@@ -67,6 +67,19 @@ versions:
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- Fix typos in description of qc.shlsat and qc.shlusat instructions
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- Fix bug in qc.shlsat that caused wrong IDL code result
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- Fix clobbering of saturation results in [add|addu|sub]sat instructions
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- version: "0.6.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
81+
- Fix wrong mantissa bit selection in qc.norm, qc.normu and qc.normeu instructions
82+
- Fix wrong exponent calculation in qc.normeu instruction
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description: |
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The Xqcia extension includes eleven instructions to perform integer arithmetic.
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‎arch_overlay/qc_iu/ext/Xqcibm.yaml‎

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@@ -88,6 +88,23 @@ versions:
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- Fix IDL code and description to look correct in PDF for qc.insbhr and qc.insbh instructions
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- Fix IDL code to to match description for qc.insbr instruction
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requires: { name: Zca, version: ">= 1.0.0" }
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- version: "0.7.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
102+
- Fix IDL code sign extension logic for qc.ext and qc.extd instructions
103+
- Fix IDL code sign extension logic for qc.extdpr, qc.extdprh and qc.extdr instructions
104+
- Fix IDL code and description increasing shift to 6 bit for qc.extdr and qc.extdur instructions
105+
- Fix IDL code and description increasing shift to 6 bit for qc.extdpr and qc.extdprh instructions
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- Fix IDL code and description increasing shift to 6 bit for qc.extdupr and qc.extduprh instructions
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requires: { name: Zca, version: ">= 1.0.0" }
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description: |
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The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
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include insertion and extraction.

‎arch_overlay/qc_iu/ext/Xqcicli.yaml‎

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@@ -28,6 +28,18 @@ versions:
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email: [email protected]
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changes:
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- Add information about instruction formats of each instruction
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- version: "0.3.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
37+
email: [email protected]
38+
- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix IDL code sign extension logic for qc.lieq instruction
3143
description: |
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The Xqcicli extension includes twelve instructions that conditionally
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load an immediate value.

‎arch_overlay/qc_iu/ext/Xqciint.yaml‎

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@@ -80,6 +80,19 @@ versions:
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changes:
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- Add stack checks to qc.c.mienter, qc.c.mienter.nest, qc.c.mileaveret
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requires: { name: Zca, version: ">= 1.0.0" }
83+
- version: "0.6.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
88+
company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
93+
changes:
94+
- Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions
95+
requires: { name: Zca, version: ">= 1.0.0" }
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description: |
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The Xqciint extension includes eleven instructions to accelerate interrupt
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servicing by performing common actions during ISR prologue/epilogue.

‎arch_overlay/qc_iu/ext/Xqcilo.yaml‎

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@@ -29,6 +29,18 @@ versions:
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changes:
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- Add information about instruction formats of each instruction
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requires: { name: Zca, version: ">= 1.0.0" }
32+
- version: "0.3.0"
33+
state: frozen
34+
ratification_date: null
35+
contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
38+
email: [email protected]
39+
- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
42+
changes:
43+
- Fix IDL code sign extension logic for qc.e.lb and qc.e.lh instructions
3244
description: |
3345
The Xqcilo extension includes eight 48-bit load/stores instructions that use an offset
3446
larger than can be found in the base RISC-V ISA.

‎arch_overlay/qc_iu/ext/Xqcilsm.yaml‎

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@@ -52,6 +52,18 @@ versions:
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email: [email protected]
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changes:
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- Fix encoding of qc.swmi
55+
- version: "0.5.0"
56+
state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
66+
- Fix IDL code and description of qc.setwm instruction to state that number of words written 0..31.
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description: |
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The Xqcilsm extension includes six instructions that transfer multiple values
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between registers and memory.

‎arch_overlay/qc_iu/inst/Xqci/qc.c.mnret.yaml‎

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@@ -30,6 +30,12 @@ operation(): |
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CSR[qc.mcause].sw_write(qc_mcause_val_masked |
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(1<<28) | (mnpie_val<<26) | (1<<30) |
3232
(mnpil_val << 12) | (0xF << 20));
33+
if (CSR[mnstatus].MNPP != 2'b11) {
34+
CSR[mstatus].MPRV = 0;
35+
if (implemented?(ExtensionName::Smdbltrp)) {
36+
CSR[mstatush].MDT = 1'b0;
37+
}
38+
}
3339
if (CSR[mnstatus].MNPP == 2'b00) {
3440
set_mode(PrivilegeMode::U);
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} else if (CSR[mnstatus].MNPP == 2'b01) {

‎arch_overlay/qc_iu/inst/Xqci/qc.c.mret.yaml‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,11 +28,16 @@ operation(): |
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Bits<4> mpil_val = (qc_mcause_val >> 16) & 0xF;
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CSR[mstatus].MIE = mpie_val;
3030
CSR[mstatus].MPIE = 1'b1;
31-
CSR[mstatush].MDT = mpdt_val;
31+
if (implemented?(ExtensionName::Smdbltrp)) {
32+
CSR[mstatush].MDT = mpdt_val;
33+
}
3234
CSR[qc.mcause].sw_write(qc_mcause_val_masked |
3335
(1<<27) | (mpie_val<<26) | (0<<29) |
3436
(mpil_val << 12) | (0xF << 16));
3537
if (mpdt_val == 1'b0) {
38+
if (CSR[mstatus].MPP != 2'b11) {
39+
CSR[mstatus].MPRV = 0;
40+
}
3641
if (CSR[mstatus].MPP == 2'b00) {
3742
set_mode(PrivilegeMode::U);
3843
} else if (CSR[mstatus].MPP == 2'b01) {

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