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Xqci extension: adding Xqcisync extension (sync with non-memory-mapped devices and delay)
Signed-off-by: Albert Yosher <[email protected]>
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‎cfgs/qc_iu/arch_overlay/ext/Xqci.yaml‎

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@@ -105,6 +105,7 @@ versions:
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changes:
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- Added Xqciio sub-extension
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- Added Xqcisim sub-extension
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- Added Xqcisync sub-extension
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- Fix description of qc.shladd instruction
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- Fix description and functionality of qc.c.extu instruction
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- Fix description and functionality of qc.wrapi instruction
@@ -129,6 +130,7 @@ versions:
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- [Xqcilsm, "0.3.0"]
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- [Xqcisim, "0.1.0"]
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- [Xqcisls, "0.2.0"]
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- [Xqcisync, "0.1.0"]
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requires:
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name: Zca
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version: ">= 1.0.0"

‎cfgs/qc_iu/arch_overlay/ext/Xqcisync.yaml‎

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# yaml-language-server: $schema=../../../../schemas/ext_schema.json
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$schema: ext_schema.json#
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kind: extension
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name: Xqcisync
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type: unprivileged
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long_name: Qualcomm non-memory-mapped devices synchronization and delay
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versions:
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- version: "0.1.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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description: |
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The Xqcisync extension includes nine instructions, eight for non-memory-mapped devices synchronization and delay instruction.
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Synchronization instructions are kind of IO fences that work with special devices synchronization signals.
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doc_license:
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name: Creative Commons Attribution 4.0 International License
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url: https://creativecommons.org/licenses/by/4.0/
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company:
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name: Qualcomm Technologies, Inc.
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url: https://qualcomm.com

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.delay.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.c.delay
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long_name: Delay execution for immediate amount of cycles
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description: |
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Delay execution for amount of cycles provided as immediate argument
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Instruction encoded in CI instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: ""
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base: 32
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encoding:
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match: "000000000-----10"
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variables:
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- name: imm
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location: 6-2
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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delay(imm);

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.sync.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.c.sync
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long_name: Non-memory-mapped device read-after-write synchronization to completion
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description: |
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This synchronization instruction delays execution till last read (input)
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from non-memory-mapped device transactions are completed for specified devices.
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As well, instruction implies fence.tso functionality for all memory accesses.
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Immediate argument is 3-bit encoding of 5-bit bitmask field
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that specifies up to five pre-defined devices.
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Values of bitmask encoding supported: 0,1,2,4,8,16,15,31
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Instruction encoded in CB instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: " slist"
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base: 32
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encoding:
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match: "100000---0000001"
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variables:
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- name: slist
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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Bits<5> bitmask;
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if (slist == 0) {
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bitmask = 0;
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} else if (slist < 6) {
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XReg shift = slist - 1;
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bitmask = (1 << shift);
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} else {
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XReg shift = slist - 2;
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bitmask = (1 << shift) - 1;
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}
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fence_tso();
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sync_read_after_write_device(true,bitmask);

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncr.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.c.syncr
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long_name: Non-memory-mapped device read-after-write synchronization
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description: |
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This synchronization instruction delays execution till last read (input)
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from non-memory-mapped device transactions are started for specified devices.
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As well, instruction implies fence.tso functionality for all memory accesses.
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Immediate argument is 3-bit encoding of 5-bit bitmask field
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that specifies up to five pre-defined devices.
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Values of bitmask encoding supported: 0,1,2,4,8,16,15,31
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Instruction encoded in CB instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: " slist"
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base: 32
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encoding:
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match: "100001---0000001"
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variables:
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- name: slist
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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Bits<5> bitmask;
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if (slist == 0) {
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bitmask = 0;
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} else if (slist < 6) {
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XReg shift = slist - 1;
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bitmask = (1 << shift);
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} else {
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XReg shift = slist - 2;
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bitmask = (1 << shift) - 1;
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}
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fence_tso();
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sync_read_after_write_device(false,bitmask);

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwf.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.c.syncwf
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long_name: Non-memory-mapped device write-after-read synchronization
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description: |
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This synchronization instruction delays execution till last write (output)
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to non-memory-mapped device transactions are started for specified devices.
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As well, instruction implies fence.tso functionality for all memory accesses.
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Immediate argument is 3-bit encoding of 5-bit bitmask field
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that specifies up to five pre-defined devices.
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Values of bitmask encoding supported: 0,1,2,4,8,16,15,31
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Instruction encoded in CB instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: " slist"
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base: 32
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encoding:
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match: "100100---0000001"
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variables:
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- name: slist
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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Bits<5> bitmask;
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if (slist == 0) {
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bitmask = 0;
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} else if (slist < 6) {
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XReg shift = slist - 1;
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bitmask = (1 << shift);
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} else {
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XReg shift = slist - 2;
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bitmask = (1 << shift) - 1;
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}
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fence_tso();
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sync_write_after_read_device(false,bitmask);

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.syncwl.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.c.syncwl
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long_name: Non-memory-mapped device write-after-read synchronization to completion
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description: |
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This synchronization instruction delays execution till last write (output)
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to non-memory-mapped device transactions are completed for specified devices.
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As well, instruction implies fence.tso functionality for all memory accesses.
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Immediate argument is 3-bit encoding of 5-bit bitmask field
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that specifies up to five pre-defined devices.
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Values of bitmask encoding supported: 0,1,2,4,8,16,15,31
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Instruction encoded in CB instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: " slist"
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base: 32
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encoding:
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match: "100101---0000001"
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variables:
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- name: slist
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location: 9-7
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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Bits<5> bitmask;
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if (slist == 0) {
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bitmask = 0;
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} else if (slist < 6) {
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XReg shift = slist - 1;
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bitmask = (1 << shift);
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} else {
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XReg shift = slist - 2;
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bitmask = (1 << shift) - 1;
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}
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fence_tso();
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sync_write_after_read_device(true,bitmask);

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.sync.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.sync
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long_name: Non-memory-mapped device read-after-write synchronization to completion
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description: |
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This synchronization instruction delays execution till last read (input)
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from non-memory-mapped device transactions are completed for specified devices.
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As well, instruction implies fence.tso functionality for all memory accesses.
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Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices.
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Instruction encoded in I instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: " imm"
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base: 32
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encoding:
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match: 0001000-----00000011000000010011
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variables:
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- name: imm
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location: 24-20
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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fence_tso();
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sync_read_after_write_device(true,imm);

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncr.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.syncr
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long_name: Non-memory-mapped device read-after-write synchronization
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description: |
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This synchronization instruction delays execution till last read (input)
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from non-memory-mapped device transactions are started for specified devices.
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As well, instruction implies fence.tso functionality for all memory accesses.
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Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices.
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Instruction encoded in I instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: " imm"
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base: 32
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encoding:
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match: 0010000-----00000011000000010011
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variables:
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- name: imm
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location: 24-20
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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fence_tso();
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sync_read_after_write_device(false,imm);

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.syncwf.yaml‎

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# yaml-language-server: $schema=../../../schemas/inst_schema.json
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$schema: inst_schema.json#
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kind: instruction
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name: qc.syncwf
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long_name: Non-memory-mapped device write-after-read synchronization
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description: |
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This synchronization instruction delays execution till last write (output)
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to non-memory-mapped device transactions are started for specified devices.
10+
As well, instruction implies fence.tso functionality for all memory accesses.
11+
Immediate argument is 5-bit bitmask field that specifies up to five pre-defined devices.
12+
Instruction encoded in I instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcisync
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assembly: " imm"
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base: 32
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encoding:
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match: 0100000-----00000011000000010011
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variables:
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- name: imm
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location: 24-20
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access:
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s: always
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u: always
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vs: always
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vu: always
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operation(): |
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fence_tso();
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sync_write_after_read_device(false,imm);

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