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Merge branch 'main' into dev/kbroch/fix-py-fstring-double-quotes
2 parents 56b9e0a + 5fda047 commit 2a3cc1f

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arch/inst/A/sc.d.yaml

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with both bits clear, but may result in lower performance.
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definedBy:
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anyOf: [A, Zalrsc]
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base: 64
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assembly: xd, xs2, xs1
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encoding:
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match: 00011------------011-----0101111

arch/inst/C/c.ld.yaml

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anyOf:
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- C
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- Zca
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base: 64
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assembly: xd, imm(xs1)
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encoding:
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match: 011-----------00

arch/inst/C/c.sd.yaml

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anyOf:
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- C
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- Zca
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base: 64
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assembly: xs2, imm(xs1)
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encoding:
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match: 111-----------00

arch/inst/C/c.slli.yaml

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anyOf:
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- C
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- Zca
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base: 64
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assembly: xd, shamt
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encoding:
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match: 000-----------10

arch/inst/C/c.srai.yaml

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anyOf:
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- C
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- Zca
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base: 64
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assembly: xd, shamt
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encoding:
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match: 100-01--------01

arch/inst/C/c.srli.yaml

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anyOf:
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- C
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- Zca
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base: 64
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assembly: xd, shamt
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encoding:
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match: 100-00--------01

arch/inst/M/divuw.yaml

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If the value in rs2 is zero, rd is written with all 1s.
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definedBy: M
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base: 64
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assembly: xd, xs1, xs2
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encoding:
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match: 0000001----------101-----0111011

arch/inst/M/divw.yaml

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Division resulting in signed overflow (when most negative number is divided by -1)
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will put the most negative number into rd;
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definedBy: M
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base: 64
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assembly: xd, xs1, xs2
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encoding:
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match: 0000001----------100-----0111011

arch/inst/M/mulw.yaml

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an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U].
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definedBy:
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anyOf: [M, Zmmul]
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base: 64
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assembly: xd, xs1, xs2
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encoding:
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match: 0000001----------000-----0111011

arch/inst/M/remuw.yaml

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If the value in rs2 is zero, rd gets the sign-extended value in rs1.
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definedBy: M
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base: 64
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assembly: xd, xs1, xs2
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encoding:
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match: 0000001----------111-----0111011

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