Xqci (Xqciint) extensiion: Fix IDL code of qc.c.mileaveret instruction to match Smdbltrp behaviour (#618)

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

arch_overlay/qc_iu/ext/Xqci.yaml

@@ -312,6 +312,40 @@ versions:
   requires:
     name: Zca
     version: ">= 1.0.0"
+- version: "0.10.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mileaveret instruction
+  implies:
+  - { name: Xqcia, version: "0.6.0" }
+  - { name: Xqciac, version: "0.3.0" }
+  - { name: Xqcibi, version: "0.2.0" }
+  - { name: Xqcibm, version: "0.7.0" }
+  - { name: Xqcicli, version: "0.3.0" }
+  - { name: Xqcicm, version: "0.2.0" }
+  - { name: Xqcics, version: "0.2.0" }
+  - { name: Xqcicsr, version: "0.3.0" }
+  - { name: Xqciint, version: "0.7.0" }
+  - { name: Xqciio, version: "0.1.0" }
+  - { name: Xqcilb, version: "0.2.0" }
+  - { name: Xqcili, version: "0.2.0" }
+  - { name: Xqcilia, version: "0.2.0" }
+  - { name: Xqcilo, version: "0.3.0" }
+  - { name: Xqcilsm, version: "0.5.0" }
+  - { name: Xqcisim, version: "0.2.0" }
+  - { name: Xqcisls, version: "0.2.0" }
+  - { name: Xqcisync, version: "0.2.0" }
+  requires:
+    name: Zca
+    version: ">= 1.0.0"
 description: |
   The Xqci extension includes a set of instructions that improve RISC-V code density and
   performance in microontrollers. It fills several gaps:

arch_overlay/qc_iu/ext/Xqciint.yaml

@@ -93,6 +93,19 @@ versions:
   changes:
     - Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mret and qc.c.mnret instructions
   requires: { name: Zca, version: ">= 1.0.0" }
+- version: "0.7.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix IDL code for Smdbltrp and Smrnmi spec compatibility for qc.c.mileaveret instruction
+  requires: { name: Zca, version: ">= 1.0.0" }
 description: |
   The Xqciint extension includes eleven instructions to accelerate interrupt
   servicing by performing common actions during ISR prologue/epilogue.

arch_overlay/qc_iu/inst/Xqci/qc.c.mileaveret.yaml

@@ -53,11 +53,16 @@ operation(): |
     Bits<4> mpil_val = (qc_mcause_val >> 16) & 0xF;
     CSR[mstatus].MIE = mpie_val;
     CSR[mstatus].MPIE = 1'b1;
-    CSR[mstatush].MDT = mpdt_val;
+    if (implemented?(ExtensionName::Smdbltrp)) {
+      CSR[mstatush].MDT = mpdt_val;
+    }
     CSR[qc.mcause].sw_write(qc_mcause_val_masked |
                             (1<<27) | (mpie_val<<26) | (0<<29) |
                             (mpil_val << 12) | (0xF << 16));
     if (mpdt_val == 1'b0) {
+      if (CSR[mstatus].MPP != 2'b11) {
+        CSR[mstatus].MPRV = 0;
+      }
       if (CSR[mstatus].MPP == 2'b00) {
         set_mode(PrivilegeMode::U);
       } else if (CSR[mstatus].MPP == 2'b01) {
@@ -77,6 +82,12 @@ operation(): |
     CSR[qc.mcause].sw_write(qc_mcause_val_masked |
                             (1<<28) | (mnpie_val<<26) | (1<<30) |
                             (mnpil_val << 12) | (0xF << 20));
+    if (CSR[mnstatus].MNPP != 2'b11) {
+      CSR[mstatus].MPRV = 0;
+      if (implemented?(ExtensionName::Smdbltrp)) {
+        CSR[mstatush].MDT = 1'b0;
+      }
+    }
     if (CSR[mnstatus].MNPP == 2'b00) {
       set_mode(PrivilegeMode::U);
     } else if (CSR[mnstatus].MNPP == 2'b01) {