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This certification class specifies requirements for microcontrollers.
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It targets microcontrollers running low-level software on an RTOS or bare-metal.
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This CRD is not intended for the smallest possible microcontrollers but rather for applications
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benefiting from a standardized microcontroller.
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See the https://docs.google.com/document/d/133SZKc18tLsQcT1o6gEmBUkjwrtg2ow63me54RQ1jiY[RISC-V CRDs]
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document for information relevant to all RISC-V CRDs.
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$schema: cert_class_schema.json#
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kind: certificate class
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name: MC
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long_name: Microcontroller Certificate Class
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naming_scheme: |
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The MC (M = Microcontroller, C = Certificate) has the following naming scheme (suffixes after MC
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are optional but in the below order):
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introduction: |
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This certification class specifies requirements for microcontrollers.
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It targets microcontrollers running low-level software on an RTOS or bare-metal.
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This CRD is not intended for the smallest possible microcontrollers but rather for applications
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benefiting from a standardized microcontroller.
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See the https://docs.google.com/document/d/133SZKc18tLsQcT1o6gEmBUkjwrtg2ow63me54RQ1jiY[RISC-V CRDs]
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document for information relevant to all RISC-V CRDs.
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MC<model>[v<version>]
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naming_scheme: |
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The MC (M = Microcontroller, C = Certificate) has the following naming scheme (suffixes after MC
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are optional but in the below order):
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Where:
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MC<model>[v<version>]
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* Left & right square braces denote optional.
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* \<model> is a 3 digit integer. It is changed only when mandatory extensions are added to a CRD.
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** The one's digit is incremented when a small mandatory extension is added (e.g., Zicond)
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** The ten's digit is incremented when a medium mandatory extension is addded (e.g., PMP)
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** The hundreds's digit is incremented when a large mandatory extension is addded (e.g., V or H)
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* \<version> is a semantic version (see semver.org) formatted as <major>[.<minor>.[patch]]. If \<version> is omitted, the reference applies equally to all versions.
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** A <major> release indicates support for a new optional extension.
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** A <minor> release indicates one or more of the following changes to the certification tests associated with the CRD.
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*** Fix test bug or increase test coverage
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*** Add more allowed parameter values
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*** Support new extension version
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** A <patch> release indicates just CRD specification changes without any difference in functional behavior
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Where:
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mandatory_priv_modes:
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- M
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* Left & right square braces denote optional.
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* \<model> is a 3 digit integer. It is changed only when mandatory extensions are added to a CRD.
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** The one's digit is incremented when a small mandatory extension is added (e.g., Zicond)
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** The ten's digit is incremented when a medium mandatory extension is addded (e.g., PMP)
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** The hundreds's digit is incremented when a large mandatory extension is addded (e.g., V or H)
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* \<version> is a semantic version (see semver.org) formatted as <major>[.<minor>.[patch]]. If \<version> is omitted, the reference applies equally to all versions.
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** A <major> release indicates support for a new optional extension.
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** A <minor> release indicates one or more of the following changes to the certification tests associated with the CRD.
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*** Fix test bug or increase test coverage
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*** Add more allowed parameter values
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*** Support new extension version
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** A <patch> release indicates just CRD specification changes without any difference in functional behavior
- First version after moving non-microcontroller content in this document to a new document
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called “RISC-V CRDs (Certification Requirement Documents)”
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- Change MC100 Unpriv ISA spec from
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“https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
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2016” to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
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former isn't ratified by the latter is the oldest ratified version.
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- Added requirements for WFI instruction
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- Added requirements related to msip memory-mapped register
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- revision: "0.6"
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date: 2024-07-11
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changes:
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- Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
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- Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
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- Added a table showing the mapping from MC version to ISA manuals.
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- Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller
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was ratified at that time and isn’t anticipated to be the interrupt controller used by MC100 implementations.
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- Clarified MANDATORY behaviors for mie and mip CSRs
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- Removed canonical discovery recipe because the OPT-* options directly inform the certification
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tests and certification reference model of the status of the various options. Also, canonical
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discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
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potentially illegal values to CSR fields.
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- Added more options for interrupts
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- Moved non-microcontroller content in this document to a new document called “RISC-V Certification Plans”
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- revision: "0.5"
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date: 2024-06-03
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changes:
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- Renamed to “RISC-V Microcontroller Certification Plan” based on Jason’s recommendation
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- Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
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these are mandatory in M-mode v1.13 (probably older versions too, haven’t looked yet).
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- Added table showing mapping of MC versions to associated RISC-V specifications
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- revision: "0.4"
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date: 2024-06-03
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changes:
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- Added M-mode instruction requirements
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- Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
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- Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
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- revision: "0.3"
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date: 2024-05-25
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changes:
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- Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
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- revision: "0.2"
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date: 2024-05-20
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changes:
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- Very early draft
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- revision: "0.1"
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date: 2024-05-16
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changes:
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- Initial version
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revision_history:
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- revision: "0.7.0"
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date: 2024-07-29
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changes:
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- First version after moving non-microcontroller content in this document to a new document
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called "RISC-V CRDs (Certification Requirement Documents)"
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- Change MC100 Unpriv ISA spec from
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"https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
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2016"to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
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former isn't ratified by the latter is the oldest ratified version.
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- Added requirements for WFI instruction
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- Added requirements related to msip memory-mapped register
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- revision: "0.6.0"
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date: 2024-07-11
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changes:
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- Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
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- Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
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- Added a table showing the mapping from MC version to ISA manuals.
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- Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller
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was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations.
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- Clarified MANDATORY behaviors for mie and mip CSRs
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+
- Removed canonical discovery recipe because the OPT-* options directly inform the certification
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+
tests and certification reference model of the status of the various options. Also, canonical
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+
discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
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potentially illegal values to CSR fields.
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+
- Added more options for interrupts
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- Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans"
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- revision: "0.5.0"
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date: 2024-06-03
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changes:
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- Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation
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+
- Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
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these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet).
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- Added table showing mapping of MC versions to associated RISC-V specifications
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- revision: "0.4.0"
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date: 2024-06-03
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changes:
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- Added M-mode instruction requirements
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- Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
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- Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
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- revision: "0.3.0"
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date: 2024-05-25
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changes:
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- Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
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- revision: "0.2.0"
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date: 2024-05-20
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changes:
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- Very early draft
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- revision: "0.1.0"
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date: 2024-05-16
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changes:
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- Initial version
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description: |
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MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support:
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description: |
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MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support:
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* The Unprivileged ISA is RV32I with a few extensions suitable for a basic microcontroller
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* The M-mode features are those listed as mandatory in the associated RISC-V Privileged ISA manual
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* The Unprivileged ISA is RV32I with a few extensions suitable for a basic microcontroller
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* The M-mode features are those listed as mandatory in the associated RISC-V Privileged ISA manual
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Key features not included in MC100 (i.e., OUT OF SCOPE):
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Key features not included in MC100 (i.e., OUT OF SCOPE):
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