Umbrella extensions shouldn't define instructions (#435)

* Extension A doesn't define any instructions (anymore)

Some instructions claim to be defined by the "A" extension or another
extension. Extension A was split into two "sub-extensions", "Zaamo"
and "Zalrsc", then defined to simply encompass both sub-extensions.

Since these instructions are actually now defined by the sub-extensions,
the instructions should only claim to be defined by them.

Also, move the instruction YAML files from `arch/inst/A` to their
new respective directories `arch/inst/{Zaamo,Zalrsc}`.

* Extension B doesn't define any instructions (anymore)

Some instructions claim to be defined by the "B" extension.
Extension B was split into four "sub-extensions": "Zba", "Zbb",
and "Zbs", then defined to simply encompass these sub-extensions.

Additionally, ratified extensions "Zbc", "Zbkb", "Zbkc", and "Zbkx" are
under the "B" umbrella (at least in the ISA 20240411, these are all
in Chapter 28 "B" Extension for Bit Manipulation, Version 1.0.0",
but these 3 extensions are shown only as "frozen").

Since these instructions are actually now defined by the sub-extensions,
the instructions should only claim to be defined by them.

Also, move the instruction YAML files from `arch/inst/B` to their
new respective directories `arch/inst/{Zba,Zbb,Zbc,Zbs,Zbkb,Zbkc,Zbkx}`,
when there is only one defining extension.

Some instructions are defined by multiple extensions. These are
left in the `arch/inst/B` directory, for lack of an unambiguously
better location.

* Extensions Zk, Zkn, Zks don't define any instructions

Some instructions claim to be defined by the "Zk/Zkn/Zks" extensions.
Remove these claims.

Also, move the instruction YAML files from `arch/inst/Zk` to their
new respective directories `arch/inst/{Zknd,Zkne,Zbkb}`,
when there is only one defining extension.

Some instructions are defined by multiple extensions. These are
moved to the `arch/inst/Zkn` directory, for lack of an unambiguously
better location.

* Extensions Zvkn, Zvks don't define any instructions

Some instructions claim to be defined by the "Zvkn/Zvks" extensions.
Remove these claims.

Also, move some instruction YAML files to their
new respective directories `arch/inst/{Zvkned,Zvknha}`.

Author: ThinkOpenly

arch/inst/B/andn.yaml

@@ -8,7 +8,7 @@ description: |
   This instruction performs the bitwise logical AND operation between `rs1` and the
   bitwise inversion of `rs2`.
 definedBy:
-  anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 encoding:
   match: 0100000----------111-----0110011

arch/inst/B/clmul.yaml

@@ -7,7 +7,7 @@ long_name: Carry-less multiply (low-part)
 description: |
   `clmul` produces the lower half of the 2*XLEN carry-less product
 definedBy:
-  anyOf: [Zbc, Zbkc, Zk, Zkn, Zks]
+  anyOf: [Zbc, Zbkc]
 assembly: xd, xs1, xs2
 encoding:
   match: 0000101----------001-----0110011

arch/inst/B/clmulh.yaml

@@ -7,7 +7,7 @@ long_name: Carry-less multiply (high-part)
 description: |
   `clmulh` produces the upper half of the 2*XLEN carry-less product
 definedBy:
-  anyOf: [Zbc, Zbkc, Zk, Zkn, Zks]
+  anyOf: [Zbc, Zbkc]
 assembly: xd, xs1, xs2
 encoding:
   match: 0000101----------011-----0110011

arch/inst/B/orn.yaml

@@ -7,7 +7,7 @@ long_name: OR with inverted operand
 description: |
   This instruction performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.
 definedBy:
-  anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 encoding:
   match: 0100000----------110-----0110011

arch/inst/B/rev8.yaml

@@ -15,7 +15,7 @@ description: |
   and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K
   is XLEN-32 and XLEN-16, respectively.
 definedBy:
-  anyOf: [B, Zbb, Zbkb]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1
 encoding:
   RV32:

arch/inst/B/rol.yaml

@@ -7,7 +7,7 @@ long_name: Rotate left (Register)
 description: |
   This instruction performs a rotate left of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
 definedBy:
-  anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 encoding:
   match: 0110000----------001-----0110011

arch/inst/B/rolw.yaml

@@ -8,7 +8,7 @@ description: |
   This instruction performs a rotate left of the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.
   The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.
 definedBy:
-  anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 base: 64
 encoding:

arch/inst/B/ror.yaml

@@ -7,7 +7,7 @@ long_name: Rotate right (Register)
 description: |
   This instruction performs a rotate right of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
 definedBy:
-  anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 encoding:
   match: 0110000----------101-----0110011

arch/inst/B/rori.yaml

@@ -8,7 +8,7 @@ description: |
   This instruction performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.
   For RV32, the encodings corresponding to shamt[5]=1 are reserved.
 definedBy:
-  anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, shamt
 encoding:
   RV32:

arch/inst/B/roriw.yaml

@@ -9,7 +9,7 @@ description: |
   the least-significant log2(XLEN) bits of shamt. The resulting word value is sign-extended by
   copying bit 31 to all of the more-significant bits.
 definedBy:
-  anyOf: [B, Zbb, Zbkb, Zk, Zkn, Zks]
+  anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, shamt
 base: 64
 encoding: