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Merge pull request #437 from riscv-software-src/xqci
Xqci 0.6
2 parents 6e05606 + 068a4fd commit 30b07b1

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‎arch/ext/Zcd.yaml‎

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# yaml-language-server: $schema=../../schemas/ext_schema.json
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$schema: "ext_schema.json#"
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kind: extension
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name: Zcd
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long_name: Compressed instructions for double precision floating point
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description: |
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Zcd is the existing set of compressed double precision floating point loads and stores:
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`c.fld`, `c.fldsp`, `c.fsd`, `c.fsdsp`.
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type: unprivileged
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company:
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name: RISC-V International
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url: https://riscv.org
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versions:
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- version: "1.0.0"
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state: ratified
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ratification_date: 2023-04
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repositories:
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- url: https://github.com/riscv/riscv-code-size-reduction
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branch: main
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contributors:
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- name: Tariq Kurd
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- name: Ibrahim Abu Kharmeh
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- name: Torbjørn Viem Ness
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- name: Matteo Perotti
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- name: Nidal Faour
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- name: Bill Traynor
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- name: Rafael Sene
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- name: Xinlong Wu
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- name: sinan
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- name: Jeremy Bennett
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- name: Heda Chen
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- name: Alasdair Armstrong
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- name: Graeme Smecher
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- name: Nicolas Brunie
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- name: Jiawei
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requires:
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allOf:
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- anyOf:
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- { name: Zca, version: "= 1.0.0" }
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- { name: C, version: "= 1.0.0" }
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- { name: D, version: "~> 2.2.0" }

‎cfgs/qc_iu/arch_overlay/ext/Xqci.yaml‎

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requires:
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name: Zca
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version: ">= 1.0.0"
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- version: "0.6.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix encoding of qc.c.extu instruction
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- Fix encoding of qc.swmi instruction
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- Rename qc.slasat -> qc.shlsat
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- Rename qc.sllsat -> qc.shlusat
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implies:
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- [Xqcia, "0.4.0"]
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- [Xqciac, "0.2.0"]
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- [Xqcibi, "0.2.0"]
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- [Xqcibm, "0.4.0"]
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- [Xqcicli, "0.2.0"]
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- [Xqcicm, "0.2.0"]
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- [Xqcics, "0.2.0"]
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- [Xqcicsr, "0.2.0"]
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- [Xqciint, "0.2.0"]
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- [Xqcilb, "0.2.0"]
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- [Xqcili, "0.2.0"]
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- [Xqcilia, "0.2.0"]
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- [Xqcilo, "0.2.0"]
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- [Xqcilsm, "0.4.0"]
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- [Xqcisls, "0.2.0"]
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requires:
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name: Zca
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version: ">= 1.0.0"
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description: |
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The Xqci extension includes a set of instructions that improve RISC-V code density and
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performance in microontrollers. It fills several gaps:
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company:
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name: Qualcomm Technologies, Inc.
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url: https://qualcomm.com
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conflicts: [D]

‎cfgs/qc_iu/arch_overlay/ext/Xqcia.yaml‎

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email: [email protected]
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changes:
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- Fix description and functionality of qc.wrapi instruction
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- version: "0.4.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Rename qc.slasat -> qc.shlsat
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- Rename qc.sllsat -> qc.shlusat
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description: |
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The Xqcia extension includes eleven instructions to perform integer arithmetic.
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‎cfgs/qc_iu/arch_overlay/ext/Xqciac.yaml‎

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description: |
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The Xqciac extension includes three instructions to accelerate common
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address calculations.
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conflicts: [D]
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doc_license:
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name: Creative Commons Attribution 4.0 International License
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url: https://creativecommons.org/licenses/by/4.0/

‎cfgs/qc_iu/arch_overlay/ext/Xqcibm.yaml‎

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changes:
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- Fix description and functionality of qc.c.extu instruction
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requires: { name: Zca, version: ">= 1.0.0" }
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- version: "0.4.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix encoding for qc.c.extu
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requires: { name: Zca, version: ">= 1.0.0" }
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description: |
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The Xqcibm extension includes thirty eight instructions that perform bit manipulation,
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include insertion and extraction.

‎cfgs/qc_iu/arch_overlay/ext/Xqcilsm.yaml‎

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email: [email protected]
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changes:
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- Fix description of qc.swmi, qc.lwmi and qc.setwmi instructions
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- version: "0.4.0"
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state: frozen
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ratification_date: null
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contributors:
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- name: Albert Yosher
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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- name: Derek Hower
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company: Qualcomm Technologies, Inc.
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email: [email protected]
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changes:
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- Fix encoding of qc.swmi
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description: |
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The Xqcilsm extension includes six instructions that transfer multiple values
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between registers and memory.

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.extu.yaml‎

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not: [0, 1, 2, 3, 4]
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- name: rd
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location: 11-7
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not: 0
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access:
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s: always
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u: always

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.muliadd.yaml‎

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Increments `rd` by the multiplication of `rs1` and an unsigned immediate
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Instruction encoded in CL instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqciac
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allOf:
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- not:
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anyOf:
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- allOf: [C, D]
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- Zcd
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- anyOf:
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- Xqci
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- Xqciac
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base: 32
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encoding:
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match: 001-----------10

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.c.mveqz.yaml‎

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Move `rs1` to `rd` if `rd` == 0, keep `rd` value otherwise
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Instruction encoded in CL instruction format.
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definedBy:
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anyOf:
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- Xqci
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- Xqcicm
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allOf:
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- anyOf:
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- Xqci
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- Xqcicm
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- not:
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anyOf:
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- allOf: [C, D]
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- Zcd
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base: 32
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encoding:
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match: 101011---00---10

‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.slasat.yaml‎ renamed to ‎cfgs/qc_iu/arch_overlay/inst/Xqci/qc.shlsat.yaml‎

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$schema: inst_schema.json#
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kind: instruction
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name: qc.slasat
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long_name: Saturating arithmetic left shift
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name: qc.shlsat
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long_name: Saturating signed left shift
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description: |
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Left shift `rs1` by the value of `rs2`, and saturate the signed result.
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The number of words is in `length`.

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