@@ -6,7 +6,153 @@ name: mip
66long_name : Machine Interrupt Pending
77address : 0x344
88priv_mode : M
9- description : Machine Interrupt Pending bits
9+
10+ # Description is shared with mie CSR (it copies it from here).
11+ description : |
12+ The `mie` and `mip` CSRs are MXLEN-bit read/write registers used when
13+ the CLINT or PLIC interrupt controllers are present.
14+ Note that the CLINT refers to an interrupt controller
15+ used by some RISC-V implementations but isn't a ratified
16+ RISC-V International standard.
17+
18+ The `mip` CSR contains information on pending interrupts, while `mie` is the corresponding
19+ CSR containing interrupt enable bits.
20+ Interrupt cause number _i_ (as reported in the `mcause` CSR)
21+ corresponds to bit _i_ in both `mip` and `mie`.
22+ Bits 15:0 are allocated to standard interrupt causes only, while
23+ bits 16 and above are designated for platform use.
24+
25+ NOTE: Interrupts designated for platform use may be designated for custom use
26+ at the platform's discretion.
27+
28+ An interrupt _i_ will trap to M-mode (causing the privilege mode to
29+ change to M-mode) if all of the following are true:
30+
31+ * either the current privilege mode is M and the MIE bit in the `mstatus` register is
32+ set, or the current privilege mode has less privilege than M-mode;
33+ * bit _i_ is set in both `mip` and `mie`
34+ * if register `mideleg` exists, bit _i_ is not set in `mideleg`.
35+
36+ These conditions for an interrupt trap to occur must be evaluated in a
37+ bounded amount of time from when an interrupt becomes, or ceases to be,
38+ pending in `mip`, and must also be evaluated immediately following the
39+ execution of an __x__RET instruction or an explicit write to a CSR on
40+ which these interrupt trap conditions expressly depend (including `mip`,
41+ `mie`, `mstatus`, and `mideleg`).
42+
43+ Interrupts to M-mode take priority over any interrupts to lower
44+ privilege modes.
45+
46+ Each individual bit in register `mip` may be writable or may be
47+ read-only. When bit _i_ in `mip` is writable, a pending interrupt _i_
48+ can be cleared by writing 0 to this bit. If interrupt _i_ can become
49+ pending but bit _i_ in `mip` is read-only, the implementation must
50+ provide some other mechanism for clearing the pending interrupt.
51+
52+ A bit in `mie` must be writable if the corresponding interrupt can ever
53+ become pending. Bits of `mie` that are not writable must be read-only
54+ zero.
55+
56+ [NOTE]
57+ ====
58+ The machine-level interrupt registers handle a few root interrupt
59+ sources which are assigned a fixed service priority for simplicity,
60+ while separate external interrupt controllers can implement a more
61+ complex prioritization scheme over a much larger set of interrupts that
62+ are then muxed into the machine-level interrupt sources.
63+
64+ '''
65+
66+ The non-maskable interrupt is not made visible via the `mip` register as
67+ its presence is implicitly known when executing the NMI trap handler.
68+ ====
69+
70+ If supervisor mode is implemented, bits `mip`.SEIP and `mie`.SEIE are
71+ the interrupt-pending and interrupt-enable bits for supervisor-level
72+ external interrupts. SEIP is writable in `mip`, and may be written by
73+ M-mode software to indicate to S-mode that an external interrupt is
74+ pending. Additionally, the platform-level interrupt controller may
75+ generate supervisor-level external interrupts. Supervisor-level external
76+ interrupts are made pending based on the logical-OR of the
77+ software-writable SEIP bit and the signal from the external interrupt
78+ controller. When `mip` is read with a CSR instruction, the value of the
79+ SEIP bit returned in the `rd` destination register is the logical-OR of
80+ the software-writable bit and the interrupt signal from the interrupt
81+ controller, but the signal from the interrupt controller is not used to
82+ calculate the value written to SEIP. Only the software-writable SEIP bit
83+ participates in the read-modify-write sequence of a CSRRS or CSRRC
84+ instruction.
85+
86+ [NOTE]
87+ ====
88+ For example, if we name the software-writable SEIP bit `B` and the
89+ signal from the external interrupt controller `E`, then if
90+ `csrrs t0, mip, t1` is executed, `t0[9]` is written with `B || E`, then
91+ `B` is written with `B || t1[9]`. If `csrrw t0, mip, t1` is executed,
92+ then `t0[9]` is written with `B || E`, and `B` is simply written with
93+ `t1[9]`. In neither case does `B` depend upon `E`.
94+
95+ The SEIP field behavior is designed to allow a higher privilege layer to
96+ mimic external interrupts cleanly, without losing any real external
97+ interrupts. The behavior of the CSR instructions is slightly modified
98+ from regular CSR accesses as a result.
99+ ====
100+
101+ If supervisor mode is implemented, bits `mip`.STIP and `mie`.STIE are
102+ the interrupt-pending and interrupt-enable bits for supervisor-level
103+ timer interrupts. STIP is writable in `mip`, and may be written by
104+ M-mode software to deliver timer interrupts to S-mode.
105+
106+ If supervisor mode is implemented, bits `mip`.SSIP and `mie`.SSIE are
107+ the interrupt-pending and interrupt-enable bits for supervisor-level
108+ software interrupts. SSIP is writable in `mip` and may also be set to 1
109+ by a platform-specific interrupt controller.
110+
111+ <% if ext?(:Sscofpmf) - % >
112+ bits `mip`.LCOFIP and `mie`.LCOFIE
113+ are the interrupt-pending and interrupt-enable bits for local counter-overflow
114+ interrupts.
115+ LCOFIP is read-write in `mip` and reflects the occurrence of a local
116+ counter-overflow overflow interrupt request resulting from any of the
117+ `mhpmevent__n__`.OF bits being set.
118+ <% end - % >
119+
120+ Multiple simultaneous interrupts destined for M-mode are handled in the
121+ following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.
122+
123+ [NOTE]
124+ ====
125+ The machine-level interrupt fixed-priority ordering rules were developed
126+ with the following rationale.
127+
128+ Interrupts for higher privilege modes must be serviced before interrupts
129+ for lower privilege modes to support preemption.
130+
131+ The platform-specific machine-level interrupt sources in bits 16 and
132+ above have platform-specific priority, but are typically chosen to have
133+ the highest service priority to support very fast local vectored
134+ interrupts.
135+
136+ External interrupts are handled before internal (timer/software)
137+ interrupts as external interrupts are usually generated by devices that
138+ might require low interrupt service times.
139+
140+ Software interrupts are handled before internal timer interrupts,
141+ because internal timer interrupts are usually intended for time slicing,
142+ where time precision is less important, whereas software interrupts are
143+ used for inter-processor messaging. Software interrupts can be avoided
144+ when high-precision timing is required, or high-precision timer
145+ interrupts can be routed via a different interrupt path. Software
146+ interrupts are located in the lowest four bits of `mip` as these are
147+ often written by software, and this position allows the use of a single
148+ CSR instruction with a five-bit immediate.
149+ ====
150+
151+ Restricted views of the `mip` and `mie` registers appear as the `sip`
152+ and `sie` registers for supervisor level. If an interrupt is delegated
153+ to S-mode by setting a bit in the `mideleg` register, it becomes visible
154+ in the `sip` register and is maskable using the `sie` register.
155+ Otherwise, the corresponding bits in `sip` and `sie` are read-only zero.
10156length : MXLEN
11157definedBy : Sm
12158fields :
@@ -256,4 +402,4 @@ fields:
256402 <%- end - % >
257403type : RW-H
258404 reset_value : 0
259- definedBy : Sscofpmf
405+ definedBy : Sscofpmf
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