feat(data): Add a few missing pseudoinstructions (#717)

ThinkOpenly · web-flow · commit 3dfd0fed232c · 2025-05-06T19:03:43.000Z
diff --git a/arch/inst/I/addi.yaml b/arch/inst/I/addi.yaml
@@ -22,6 +22,11 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: (xd == 0 && xs1 == 0 && imm == 0)
+    to: nop
+  - when: imm == 0
+    to: mv xd,xs1
 operation(): X[xd] = X[xs1] + $signed(imm);
 
 # SPDX-SnippetBegin
diff --git a/arch/inst/I/addiw.yaml b/arch/inst/I/addiw.yaml
@@ -23,6 +23,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: imm == 0
+    to: sext.w xd,xs1
 operation(): |
   XReg operand = sext(X[xs1], 31);
   X[xd] = sext(operand + imm, 31);
diff --git a/arch/inst/I/andi.yaml b/arch/inst/I/andi.yaml
@@ -22,6 +22,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: imm == 255
+    to: zext.b
 operation(): X[xd] = X[xs1] & $signed(imm);
 
 # SPDX-SnippetBegin
diff --git a/arch/inst/I/beq.yaml b/arch/inst/I/beq.yaml
@@ -26,6 +26,9 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs2 == 0
+    to: beqz xs1,imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];
diff --git a/arch/inst/I/bge.yaml b/arch/inst/I/bge.yaml
@@ -26,6 +26,11 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: blez xs2,imm
+  - when: xs2 == 0
+    to: blez xs1,imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];
diff --git a/arch/inst/I/blt.yaml b/arch/inst/I/blt.yaml
@@ -26,6 +26,11 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs2 == 0
+    to: bltz xs1,imm
+  - when: xs1 == 0
+    to: bgtz xs2,imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];
diff --git a/arch/inst/I/bne.yaml b/arch/inst/I/bne.yaml
@@ -26,6 +26,9 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs2 == 0
+    to: bnez xs1,imm
 operation(): |
   XReg lhs = X[xs1];
   XReg rhs = X[xs2];
diff --git a/arch/inst/I/fence.yaml b/arch/inst/I/fence.yaml
@@ -198,6 +198,8 @@ hints:
 pseudoinstructions:
   - when: (pred == 1) && (succ == 0) && (xd == 0) && (xs1 == 0)
     to: pause
+  - when: (pred == 4'b1111) && (succ == 4'b1111)
+    to: fence # fence => fence iorw,iorw
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
diff --git a/arch/inst/I/jal.yaml b/arch/inst/I/jal.yaml
@@ -23,6 +23,11 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: imm == 0
+    to: j xd
+  - when: xd == x1
+    to: jal imm
 operation(): |
   XReg retrun_addr = $pc + 4;
 
diff --git a/arch/inst/I/jalr.yaml b/arch/inst/I/jalr.yaml
@@ -25,6 +25,11 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xd == 0
+    to: jr imm(xs1)
+  - when: (rd == 0 && xs1 == x1 && imm == 0)
+    to: ret
 operation(): |
   XReg returnaddr;
   returnaddr = $pc + 4;
diff --git a/arch/inst/I/slt.yaml b/arch/inst/I/slt.yaml
@@ -24,6 +24,11 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: xs2 == 0
+    to: sltz xd,xs1
+  - when: xs1 == 0
+    to: sgtz xd,xs2
 operation(): |
   XReg src1 = X[xs1];
   XReg src2 = X[xs2];
diff --git a/arch/inst/I/sltiu.yaml b/arch/inst/I/sltiu.yaml
@@ -28,6 +28,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: imm == 1
+    to: seqz xd,xs1
 operation(): |
   Bits<MXLEN> sign_extend_imm = $signed(imm);
   X[xd] = (X[xs1] < sign_extend_imm) ? 1 : 0;
diff --git a/arch/inst/I/sltu.yaml b/arch/inst/I/sltu.yaml
@@ -24,6 +24,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: xs1 == 0
+    to: snez xd,xs2
 operation(): |
   X[xd] = (X[xs1] < X[xs2]) ? 1 : 0;
 
diff --git a/arch/inst/I/sub.yaml b/arch/inst/I/sub.yaml
@@ -22,6 +22,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: xs1 == 0
+    to: neg xd,xs2
 operation(): |
   XReg t0 = X[xs1];
   XReg t1 = X[xs2];
diff --git a/arch/inst/I/subw.yaml b/arch/inst/I/subw.yaml
@@ -23,6 +23,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: xs1 == 0
+    to: negw xd,xs2
 operation(): |
   Bits<32> t0 = X[xs1][31:0];
   Bits<32> t1 = X[xs2][31:0];
diff --git a/arch/inst/I/xori.yaml b/arch/inst/I/xori.yaml
@@ -22,6 +22,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: true
+pseudoinstructions:
+  - when: $signed(imm) == -1
+    to: not xd,xs1
 operation(): X[xd] = X[xs1] ^ $signed(imm);
 
 # SPDX-SnippetBegin
diff --git a/arch/inst/Zicsr/csrrc.yaml b/arch/inst/Zicsr/csrrc.yaml
@@ -23,6 +23,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+pseudoinstructions:
+  - when: xd == 0
+    to: csrc csr,xs1
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 
diff --git a/arch/inst/Zicsr/csrrci.yaml b/arch/inst/Zicsr/csrrci.yaml
@@ -7,7 +7,7 @@ long_name: No synopsis available
 description: |
   No description available.
 definedBy: Zicsr
-assembly: rd, imm, rs1
+assembly: xd, csr, uimm
 encoding:
   match: -----------------111-----1110011
   variables:
@@ -23,6 +23,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+pseudoinstructions:
+  - when: xd == 0
+    to: csrci csr,uimm
 operation(): |
   Boolean will_write = uimm != 0;
 
diff --git a/arch/inst/Zicsr/csrrs.yaml b/arch/inst/Zicsr/csrrs.yaml
@@ -8,9 +8,9 @@ description: |
   Atomically read and set bits in a CSR.
 
   Reads the value of the CSR, zero-extends the value to `XLEN` bits,
-  and writes it to integer register `rd`. The initial value in integer
-  register `rs1` is treated as a bit mask that specifies bit positions
-  to be set in the CSR. Any bit that is high in `rs1` will cause the
+  and writes it to integer register `xd`. The initial value in integer
+  register `xs1` is treated as a bit mask that specifies bit positions
+  to be set in the CSR. Any bit that is high in `xs1` will cause the
   corresponding bit to be set in the CSR, if that CSR bit is writable.
   Other bits in the CSR are not explicitly written.
 definedBy: Zicsr
@@ -20,17 +20,22 @@ encoding:
   variables:
     - name: csr
       location: 31-20
-    - name: rs1
+    - name: xs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xs1 == 0
+    to: csrr xd,csr
+  - when: xd == 0
+    to: csrs csr,xs1
 operation(): |
-  Boolean will_write = rs1 != 0;
+  Boolean will_write = xs1 != 0;
 
   Csr csr_handle = direct_csr_lookup(csr);
 
@@ -48,11 +53,11 @@ operation(): |
   if (will_write) {
     # set bits using the mask
     # performing any WARL transformations first
-    XReg mask = X[rs1];
+    XReg mask = X[xs1];
     csr_sw_write(csr_handle, initial_csr_value | mask);
   }
 
-  X[rd] = initial_csr_value;
+  X[xd] = initial_csr_value;
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
diff --git a/arch/inst/Zicsr/csrrsi.yaml b/arch/inst/Zicsr/csrrsi.yaml
@@ -7,7 +7,7 @@ long_name: No synopsis available
 description: |
   No description available.
 definedBy: Zicsr
-assembly: rd, imm, rs1
+assembly: xd, csr, uimm
 encoding:
   match: -----------------110-----1110011
   variables:
@@ -23,6 +23,9 @@ access:
   vs: always
   vu: always
 data_independent_timing: false
+pseudoinstructions:
+  - when: xd == 0
+    to: csrsi csr,uimm
 operation(): |
   Boolean will_write = uimm != 0;
 
diff --git a/arch/inst/Zicsr/csrrw.yaml b/arch/inst/Zicsr/csrrw.yaml
@@ -8,9 +8,9 @@ description: |
   Atomically swap values in the CSRs and integer registers.
 
   Read the old value of the CSR, zero-extends the value to `XLEN` bits,
-  and then write it to integer register rd.
-  The initial value in rs1 is written to the CSR.
-  If `rd=x0`, then the instruction shall not read the CSR and shall not
+  and then write it to integer register xd.
+  The initial value in xs1 is written to the CSR.
+  If `xd=x0`, then the instruction shall not read the CSR and shall not
   cause any of the side effects that might occur on a CSR read.
 definedBy: Zicsr
 assembly: xd, imm, xs1
@@ -28,6 +28,9 @@ access:
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xd == 0
+    to: csrw csr,xs1
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 
diff --git a/arch/inst/Zicsr/csrrwi.yaml b/arch/inst/Zicsr/csrrwi.yaml
@@ -5,29 +5,32 @@ kind: instruction
 name: csrrwi
 long_name: Atomic Read/Write CSR Immediate
 description: |
-  Atomically write CSR using a 5-bit immediate, and load the previous value into 'rd'.
+  Atomically write CSR using a 5-bit immediate, and load the previous value into 'xd'.
 
   Read the old value of the CSR, zero-extends the value to `XLEN` bits,
-  and then write it to integer register rd.
+  and then write it to integer register xd.
   The 5-bit uimm field is zero-extended and written to the CSR.
-  If `rd=x0`, then the instruction shall not read the CSR and shall not
+  If `xd=x0`, then the instruction shall not read the CSR and shall not
   cause any of the side effects that might occur on a CSR read.
 definedBy: Zicsr
-assembly: rd, imm, rs1
+assembly: xd, imm, xs1
 encoding:
   match: -----------------101-----1110011
   variables:
     - name: csr
       location: 31-20
     - name: imm
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
   u: always
   vs: always
   vu: always
+pseudoinstructions:
+  - when: xd == 0
+    to: csrwi csr,imm
 operation(): |
   Csr csr_handle = direct_csr_lookup(csr);
 
@@ -40,8 +43,8 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  if (rd != 0) {
-    X[rd] = csr_sw_read(csr_handle);
+  if (xd != 0) {
+    X[xd] = csr_sw_read(csr_handle);
   }
 
   # writes the zero-extended immediate to the CSR,
