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Merge branch 'riscv-software-src:main' into add-ssqosid-csr-yaml
2 parents 253613c + 48cbf1b commit 47267ea

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‎.devcontainer/Dockerfile‎

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@@ -26,6 +26,7 @@ RUN \
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libc6-dev-riscv64-cross \
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libelf-dev \
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libgmp-dev \
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libnewlib-dev\
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libyaml-dev \
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nodejs \
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npm \

‎.pre-commit-config.yaml‎

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rev: 0.33.0
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hooks:
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- id: check-jsonschema
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name: Validate instruction files with jsonschema
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stages: [pre-commit]
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alias: check-jsonschema-inst
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files: ^arch/inst/.*\.(yaml|yml)$
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args: ["--schemafile", "schemas/inst_schema.json"]
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- id: check-jsonschema
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name: Validate CSR files with jsonschema
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stages: [pre-commit]
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alias: check-jsonschema-csr
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files: ^arch/csr/.*\.(yaml|yml)$
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args: ["--schemafile", "schemas/csr_schema.json"]
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- id: check-jsonschema
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name: Validate extension files with jsonschema
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stages: [pre-commit]
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alias: check-jsonschema-ext
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files: ^arch/ext/.*\.(yaml|yml)$
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args: ["--schemafile", "schemas/ext_schema.json"]
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- id: check-jsonschema
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name: Validate cert model files with jsonschema
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stages: [pre-commit]
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alias: check-jsonschema-cert-model
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files: ^arch/proc_cert_model/.*\.(yaml|yml)$
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args: ["--schemafile", "schemas/proc_cert_model_schema.json"]
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- id: check-jsonschema
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name: Validate cert class files with jsonschema
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stages: [pre-commit]
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alias: check-jsonschema-cert-class
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files: ^arch/proc_cert_class/.*\.(yaml|yml)$
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args: ["--schemafile", "schemas/proc_cert_class_schema.json"]
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- id: check-jsonschema
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name: Validate profile family files with jsonschema
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stages: [pre-commit]
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alias: check-jsonschema-profile-family
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files: ^arch/profile_family/.*\.(yaml|yml)$
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args: ["--schemafile", "schemas/profile_family_schema.json"]
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- id: check-jsonschema
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name: Validate profile release files with jsonschema
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stages: [pre-commit]
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alias: check-jsonschema-profile-release
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files: ^arch/profile_release/.*\.(yaml|yml)$
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args: ["--schemafile", "schemas/profile_release_schema.json"]
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# Commenting because throwing errors and not sure this is complete yet
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# - id: check-jsonschema
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# alias: check-jsonschema-manual-version

‎.vscode/launch.json‎

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},
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{
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"type": "rdbg",
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"name": "RVA20",
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"name": "RVI20",
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"request": "launch",
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"command": "bundle exec rake",
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"script": "gen:profile_release_pdf[RVA20]",
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"script": "gen:profile_release_pdf[RVI20]",
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"args": [],
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"askParameters": false
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},

‎Rakefile‎

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@@ -388,6 +388,15 @@ file "#{$root}/arch/csr/S/scounteren.yaml" => [
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File.write(t.name, insert_warning(erb.result(binding), t.prerequisites.first))
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end
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file "#{$root}/arch/csr/Sscofpmf/scountovf.yaml" => [
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"#{$root}/arch/csr/Sscofpmf/scountovf.layout",
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__FILE__
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] do |t|
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erb = ERB.new(File.read($root / "arch/csr/Sscofpmf/scountovf.layout"), trim_mode: "-")
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erb.filename = "#{$root}/arch/csr/Sscofpmf/scountovf.layout"
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File.write(t.name, insert_warning(erb.result(binding), t.prerequisites.first))
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end
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file "#{$root}/arch/csr/H/hcounteren.yaml" => [
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"#{$root}/arch/csr/H/hcounteren.layout",
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__FILE__
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Rake::Task["#{$root}/arch/csr/I/mcounteren.yaml"].invoke
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Rake::Task["#{$root}/arch/csr/S/scounteren.yaml"].invoke
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Rake::Task["#{$root}/arch/csr/Sscofpmf/scountovf.yaml"].invoke
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Rake::Task["#{$root}/arch/csr/H/hcounteren.yaml"].invoke
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Rake::Task["#{$root}/arch/csr/Zicntr/mcountinhibit.yaml"].invoke
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‎arch/csr/Smcntrpmf/mcyclecfg.yaml‎

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mcyclecfg
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long_name: Machine Cycle Counter Configuration
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address: 0x321
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priv_mode: M
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length: 64
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definedBy: Smcntrpmf
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description: |
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The `mcyclecfg` CSR is a 64-bit machine-level register that configures privilege
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mode filtering for the cycle counter. Each inhibit bit (xINH) suppresses
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counting of events in the corresponding privilege mode when set.
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| Field | Description |
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|---------|---------------------------------------------------------|
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| MINH | If set, then counting of events in M-mode is inhibited. |
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| SINH | If set, then counting of events in S/HS-mode is inhibited. |
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| UINH | If set, then counting of events in U-mode is inhibited. |
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| VSINH | If set, then counting of events in VS-mode is inhibited. |
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| VUINH | If set, then counting of events in VU-mode is inhibited. |
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When all xINH bits are zero, event counting is enabled in all modes.
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For each bit in 61:58, if the associated privilege mode is not implemented,
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the bit is read-only zero.
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Bit 63 is hardwired to 0, as these counters do not generate overflow interrupts.
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Bits [57:0] are reserved (WPRI) and read as zero.
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For RV32, the upper 32 bits of `mcyclecfg` are accessed via `mcyclecfgh` (CSR 0x721).
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Note: Although CSR address 0x320 would have been a more natural choice,
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it is already allocated to `mcountinhibit`.
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fields:
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MINH:
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location: 62
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base: 64
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type: RW
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definedBy: M
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description: If set, then counting of events in M-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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SINH:
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location: 61
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base: 64
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type: RW
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definedBy: S
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description: If set, then counting of events in S/HS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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UINH:
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location: 60
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base: 64
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type: RW
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definedBy: U
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description: If set, then counting of events in U-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VSINH:
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location: 59
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base: 64
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type: RW
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definedBy: H
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description: If set, then counting of events in VS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VUINH:
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location: 58
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base: 64
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type: RW
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definedBy: H
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description: If set, then counting of events in VU-mode is inhibited.
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reset_value: UNDEFINED_LEGAL

‎arch/csr/Smcntrpmf/mcyclecfgh.yaml‎

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: mcyclecfgh
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long_name: Machine Cycle Counter Configuration High
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address: 0x721
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priv_mode: M
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length: 32
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definedBy: Smcntrpmf
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description: |
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Upper 32 bits of the 64-bit `mcyclecfg` CSR, used for RV32 systems to access
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the privilege mode filtering inhibit bits.
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fields:
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MINH:
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alias: mcyclecfg.MINH
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location: 30
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type: RW
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definedBy: M
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description: If set, then counting of events in M-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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SINH:
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alias: mcyclecfg.SINH
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location: 29
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type: RW
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definedBy: S
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description: If set, then counting of events in S/HS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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UINH:
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alias: mcyclecfg.UINH
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location: 28
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type: RW
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definedBy: U
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description: If set, then counting of events in U-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VSINH:
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alias: mcyclecfg.VSINH
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location: 27
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type: RW
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definedBy: H
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description: If set, then counting of events in VS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VUINH:
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alias: mcyclecfg.VUINH
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location: 26
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type: RW
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definedBy: H
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description: If set, then counting of events in VU-mode is inhibited.
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reset_value: UNDEFINED_LEGAL

‎arch/csr/Smcntrpmf/minstretcfg.yaml‎

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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kind: csr
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name: minstretcfg
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long_name: Machine Instructions-Retired Counter Configuration
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address: 0x322
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priv_mode: M
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length: 64
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definedBy: Smcntrpmf
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description: |
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The `minstretcfg` CSR is a 64-bit machine-level register that configures privilege
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mode filtering for the `minstret` (Machine Instructions-Retired Counter). Each inhibit bit (xINH)
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disables counting of retired instructions in the associated privilege mode.
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| Field | Description |
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|---------|-----------------------------------------------------------|
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| MINH | If set, then counting of events in M-mode is inhibited. |
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| SINH | If set, then counting of events in S/HS-mode is inhibited. |
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| UINH | If set, then counting of events in U-mode is inhibited. |
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| VSINH | If set, then counting of events in VS-mode is inhibited. |
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| VUINH | If set, then counting of events in VU-mode is inhibited. |
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When all inhibit bits are clear, instruction retirement is counted in all privilege modes.
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For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.
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Bit 63 (OF) always reads as zero, indicating that the counter does not generate overflow interrupts.
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Bits [57:0] are reserved (WPRI) and read as zero; writes are ignored.
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For RV32 systems, the upper 32 bits of `minstretcfg` are accessible via the `minstretcfgh` CSR (0x722).
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fields:
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MINH:
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location: 62
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base: 64
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type: RW
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definedBy: M
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description: If set, then counting of events in M-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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SINH:
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location: 61
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base: 64
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type: RW
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definedBy: S
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description: If set, then counting of events in S/HS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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UINH:
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location: 60
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base: 64
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type: RW
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definedBy: U
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description: If set, then counting of events in U-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VSINH:
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location: 59
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base: 64
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type: RW
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definedBy: H
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description: If set, then counting of events in VS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VUINH:
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location: 58
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base: 64
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type: RW
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definedBy: H
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description: If set, then counting of events in VU-mode is inhibited.
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reset_value: UNDEFINED_LEGAL

‎arch/csr/Smcntrpmf/minstretcfgh.yaml‎

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: csr_schema.json#
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kind: csr
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name: minstretcfgh
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long_name: Machine Instructions-Retired Counter Configuration High
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address: 0x722
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priv_mode: M
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length: 32
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definedBy: Smcntrpmf
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description: |
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Upper 32 bits of the 64-bit `minstretcfg` CSR, used on RV32 systems to access
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privilege mode filtering inhibit bits for instruction retirement.
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fields:
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MINH:
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alias: minstretcfg.MINH
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location: 30
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type: RW
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definedBy: M
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description: If set, then counting of events in M-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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SINH:
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alias: minstretcfg.SINH
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location: 29
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type: RW
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definedBy: S
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description: If set, then counting of events in S/HS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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UINH:
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alias: minstretcfg.UINH
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location: 28
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type: RW
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definedBy: U
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description: If set, then counting of events in U-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VSINH:
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alias: minstretcfg.VSINH
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location: 27
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type: RW
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definedBy: H
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description: If set, then counting of events in VS-mode is inhibited.
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reset_value: UNDEFINED_LEGAL
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VUINH:
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alias: minstretcfg.VUINH
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location: 26
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type: RW
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definedBy: H
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description: If set, then counting of events in VU-mode is inhibited.
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reset_value: UNDEFINED_LEGAL

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