Skip to content

Commit 5d203dd

Browse files
james-ball-qualcommjames-ball-qualcomm
committed
Created $copy to copy string values like $ref. Added unit-level test. Fixed mie to be defined by Sm not I extension. Description for mip and mie is now shared mimicing ISA manual.
1 parent cd37f0b commit 5d203dd

File tree

6 files changed

+323
-212
lines changed

6 files changed

+323
-212
lines changed

‎arch/csr/mhartid.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ mhartid:
66
priv_mode: M
77
length: MXLEN
88
description: Reports the unique hart-specific ID in the system.
9-
definedBy: I
9+
definedBy: Sm
1010
fields:
1111
ID:
1212
location_rv32: 31-0

‎arch/csr/mie.yaml‎

Lines changed: 2 additions & 141 deletions
Original file line numberDiff line numberDiff line change
@@ -5,147 +5,8 @@ mie:
55
address: 0x304
66
priv_mode: M
77
length: MXLEN
8-
definedBy: I
9-
description: |
10-
Per-type interrupt enables.
11-
12-
For a detailed description of interrupt handling, see <%= link_to(:section, 'sec:interrupts') %>.
13-
14-
The `mie` register is an
15-
MXLEN-bit read/write register containing interrupt enable bits.
16-
Interrupt cause number _i_ (as reported in CSR `mcause`) corresponds with
17-
bit _i_ in
18-
`mie`. Bits 15:0 are allocated to standard interrupt causes only, while
19-
bits 16 and above are designated for platform use.
20-
21-
NOTE: Interrupts designated for platform use may be designated for custom use
22-
at the platform's discretion.
23-
24-
An interrupt _i_ will trap to M-mode (causing the privilege mode to
25-
change to M-mode) if all of the following are true:
26-
27-
* either the current privilege mode is M and the MIE bit in the
28-
`mstatus` register is set, or the current privilege mode has less
29-
privilege than M-mode;
30-
* bit _i_ is set in both `mip` and `mie`;
31-
* if register `mideleg` exists, bit _i_ is not set in `mideleg`.
32-
33-
These conditions for an interrupt trap to occur must be evaluated in a
34-
bounded amount of time from when an interrupt becomes, or ceases to be,
35-
pending in `mip`, and must also be evaluated immediately following the
36-
execution of an __x__RET instruction or an explicit write to a CSR on
37-
which these interrupt trap conditions expressly depend (including `mip`,
38-
`mie`, `mstatus`, and `mideleg`).
39-
40-
Interrupts to M-mode take priority over any interrupts to lower
41-
privilege modes.
42-
43-
A bit in `mie` must be writable if the corresponding interrupt can ever
44-
become pending. Bits of `mie` that are not writable must be read-only
45-
zero.
46-
47-
[NOTE]
48-
====
49-
The machine-level interrupt registers handle a few root interrupt
50-
sources which are assigned a fixed service priority for simplicity,
51-
while separate external interrupt controllers can implement a more
52-
complex prioritization scheme over a much larger set of interrupts that
53-
are then muxed into the machine-level interrupt sources.
54-
55-
'''
56-
57-
The non-maskable interrupt is not made visible via the `mip` register as
58-
its presence is implicitly known when executing the NMI trap handler.
59-
====
60-
61-
If supervisor mode is implemented, bits `mip`.SEIP and `mie`.SEIE are
62-
the interrupt-pending and interrupt-enable bits for supervisor-level
63-
external interrupts. SEIP is writable in `mip`, and may be written by
64-
M-mode software to indicate to S-mode that an external interrupt is
65-
pending. Additionally, the platform-level interrupt controller may
66-
generate supervisor-level external interrupts. Supervisor-level external
67-
interrupts are made pending based on the logical-OR of the
68-
software-writable SEIP bit and the signal from the external interrupt
69-
controller. When `mip` is read with a CSR instruction, the value of the
70-
SEIP bit returned in the `rd` destination register is the logical-OR of
71-
the software-writable bit and the interrupt signal from the interrupt
72-
controller, but the signal from the interrupt controller is not used to
73-
calculate the value written to SEIP. Only the software-writable SEIP bit
74-
participates in the read-modify-write sequence of a CSRRS or CSRRC
75-
instruction.
76-
77-
[NOTE]
78-
====
79-
For example, if we name the software-writable SEIP bit `B` and the
80-
signal from the external interrupt controller `E`, then if
81-
`csrrs t0, mip, t1` is executed, `t0[9]` is written with `B || E`, then
82-
`B` is written with `B || t1[9]`. If `csrrw t0, mip, t1` is executed,
83-
then `t0[9]` is written with `B || E`, and `B` is simply written with
84-
`t1[9]`. In neither case does `B` depend upon `E`.
85-
86-
The SEIP field behavior is designed to allow a higher privilege layer to
87-
mimic external interrupts cleanly, without losing any real external
88-
interrupts. The behavior of the CSR instructions is slightly modified
89-
from regular CSR accesses as a result.
90-
====
91-
92-
If supervisor mode is implemented, bits `mip`.STIP and `mie`.STIE are
93-
the interrupt-pending and interrupt-enable bits for supervisor-level
94-
timer interrupts. STIP is writable in `mip`, and may be written by
95-
M-mode software to deliver timer interrupts to S-mode.
96-
97-
If supervisor mode is implemented, bits `mip`.SSIP and `mie`.SSIE are
98-
the interrupt-pending and interrupt-enable bits for supervisor-level
99-
software interrupts. SSIP is writable in `mip` and may also be set to 1
100-
by a platform-specific interrupt controller.
101-
102-
<%- if ext?(:Sscofpmf) -%>
103-
Bits `mip`.LCOFIP and `mie`.LCOFIE
104-
are the interrupt-pending and interrupt-enable bits for local counter-overflow
105-
interrupts.
106-
LCOFIP is read-write in `mip` and reflects the occurrence of a local
107-
counter-overflow overflow interrupt request resulting from any of the
108-
`mhpmevent__n__`.OF bits being set.
109-
If the Sscofpmf extension is not implemented, `mip`.LCOFIP and `mie`.LCOFIE are
110-
read-only zeros.
111-
<%- end -%>
112-
113-
Multiple simultaneous interrupts destined for M-mode are handled in the
114-
following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.
115-
116-
[NOTE]
117-
====
118-
The machine-level interrupt fixed-priority ordering rules were developed
119-
with the following rationale.
120-
121-
Interrupts for higher privilege modes must be serviced before interrupts
122-
for lower privilege modes to support preemption.
123-
124-
The platform-specific machine-level interrupt sources in bits 16 and
125-
above have platform-specific priority, but are typically chosen to have
126-
the highest service priority to support very fast local vectored
127-
interrupts.
128-
129-
External interrupts are handled before internal (timer/software)
130-
interrupts as external interrupts are usually generated by devices that
131-
might require low interrupt service times.
132-
133-
Software interrupts are handled before internal timer interrupts,
134-
because internal timer interrupts are usually intended for time slicing,
135-
where time precision is less important, whereas software interrupts are
136-
used for inter-processor messaging. Software interrupts can be avoided
137-
when high-precision timing is required, or high-precision timer
138-
interrupts can be routed via a different interrupt path. Software
139-
interrupts are located in the lowest four bits of `mip` as these are
140-
often written by software, and this position allows the use of a single
141-
CSR instruction with a five-bit immediate.
142-
====
143-
144-
Restricted views of the `mip` and `mie` registers appear as the `sip`
145-
and `sie` registers for supervisor level. If an interrupt is delegated
146-
to S-mode by setting a bit in the `mideleg` register, it becomes visible
147-
in the `sip` register and is maskable using the `sie` register.
148-
Otherwise, the corresponding bits in `sip` and `sie` are read-only zero.
8+
definedBy: Sm
9+
description: "$copy: mip.yaml#/mip/description"
14910
fields:
15011
SSIE:
15112
location: 1

‎arch/csr/mip.yaml‎

Lines changed: 140 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,146 @@ mip:
44
long_name: Machine Interrupt Pending
55
address: 0x344
66
priv_mode: M
7-
description: Machine Interrupt Pending bits
7+
description: |
8+
The `mip` register is an MXLEN-bit read/write register containing
9+
information on pending interrupts, while `mie` is the corresponding
10+
MXLEN-bit read/write register containing interrupt enable bits.
11+
Interrupt cause number _i_ (as reported in CSR `mcause`)
12+
corresponds with bit _i_ in both `mip` and
13+
`mie`. Bits 15:0 are allocated to standard interrupt causes only, while
14+
bits 16 and above are designated for platform use.
15+
16+
NOTE: Interrupts designated for platform use may be designated for custom use
17+
at the platform's discretion.
18+
19+
An interrupt _i_ will trap to M-mode (causing the privilege mode to
20+
change to M-mode) if all of the following are true:
21+
22+
* either the current privilege mode is M and the MIE bit in the `mstatus` register is
23+
set, or the current privilege mode has less privilege than M-mode;
24+
* bit _i_ is set in both `mip` and `mie`
25+
* if register `mideleg` exists, bit _i_ is not set in `mideleg`.
26+
27+
These conditions for an interrupt trap to occur must be evaluated in a
28+
bounded amount of time from when an interrupt becomes, or ceases to be,
29+
pending in `mip`, and must also be evaluated immediately following the
30+
execution of an __x__RET instruction or an explicit write to a CSR on
31+
which these interrupt trap conditions expressly depend (including `mip`,
32+
`mie`, `mstatus`, and `mideleg`).
33+
34+
Interrupts to M-mode take priority over any interrupts to lower
35+
privilege modes.
36+
37+
Each individual bit in register `mip` may be writable or may be
38+
read-only. When bit _i_ in `mip` is writable, a pending interrupt _i_
39+
can be cleared by writing 0 to this bit. If interrupt _i_ can become
40+
pending but bit _i_ in `mip` is read-only, the implementation must
41+
provide some other mechanism for clearing the pending interrupt.
42+
43+
A bit in `mie` must be writable if the corresponding interrupt can ever
44+
become pending. Bits of `mie` that are not writable must be read-only
45+
zero.
46+
47+
[NOTE]
48+
====
49+
The machine-level interrupt registers handle a few root interrupt
50+
sources which are assigned a fixed service priority for simplicity,
51+
while separate external interrupt controllers can implement a more
52+
complex prioritization scheme over a much larger set of interrupts that
53+
are then muxed into the machine-level interrupt sources.
54+
55+
'''
56+
57+
The non-maskable interrupt is not made visible via the `mip` register as
58+
its presence is implicitly known when executing the NMI trap handler.
59+
====
60+
61+
If supervisor mode is implemented, bits `mip`.SEIP and `mie`.SEIE are
62+
the interrupt-pending and interrupt-enable bits for supervisor-level
63+
external interrupts. SEIP is writable in `mip`, and may be written by
64+
M-mode software to indicate to S-mode that an external interrupt is
65+
pending. Additionally, the platform-level interrupt controller may
66+
generate supervisor-level external interrupts. Supervisor-level external
67+
interrupts are made pending based on the logical-OR of the
68+
software-writable SEIP bit and the signal from the external interrupt
69+
controller. When `mip` is read with a CSR instruction, the value of the
70+
SEIP bit returned in the `rd` destination register is the logical-OR of
71+
the software-writable bit and the interrupt signal from the interrupt
72+
controller, but the signal from the interrupt controller is not used to
73+
calculate the value written to SEIP. Only the software-writable SEIP bit
74+
participates in the read-modify-write sequence of a CSRRS or CSRRC
75+
instruction.
76+
77+
[NOTE]
78+
====
79+
For example, if we name the software-writable SEIP bit `B` and the
80+
signal from the external interrupt controller `E`, then if
81+
`csrrs t0, mip, t1` is executed, `t0[9]` is written with `B || E`, then
82+
`B` is written with `B || t1[9]`. If `csrrw t0, mip, t1` is executed,
83+
then `t0[9]` is written with `B || E`, and `B` is simply written with
84+
`t1[9]`. In neither case does `B` depend upon `E`.
85+
86+
The SEIP field behavior is designed to allow a higher privilege layer to
87+
mimic external interrupts cleanly, without losing any real external
88+
interrupts. The behavior of the CSR instructions is slightly modified
89+
from regular CSR accesses as a result.
90+
====
91+
92+
If supervisor mode is implemented, bits `mip`.STIP and `mie`.STIE are
93+
the interrupt-pending and interrupt-enable bits for supervisor-level
94+
timer interrupts. STIP is writable in `mip`, and may be written by
95+
M-mode software to deliver timer interrupts to S-mode.
96+
97+
If supervisor mode is implemented, bits `mip`.SSIP and `mie`.SSIE are
98+
the interrupt-pending and interrupt-enable bits for supervisor-level
99+
software interrupts. SSIP is writable in `mip` and may also be set to 1
100+
by a platform-specific interrupt controller.
101+
102+
<% if ext?(:Sscofpmf) -%>
103+
bits `mip`.LCOFIP and `mie`.LCOFIE
104+
are the interrupt-pending and interrupt-enable bits for local counter-overflow
105+
interrupts.
106+
LCOFIP is read-write in `mip` and reflects the occurrence of a local
107+
counter-overflow overflow interrupt request resulting from any of the
108+
`mhpmevent__n__`.OF bits being set.
109+
<% end -%>
110+
111+
Multiple simultaneous interrupts destined for M-mode are handled in the
112+
following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.
113+
114+
[NOTE]
115+
====
116+
The machine-level interrupt fixed-priority ordering rules were developed
117+
with the following rationale.
118+
119+
Interrupts for higher privilege modes must be serviced before interrupts
120+
for lower privilege modes to support preemption.
121+
122+
The platform-specific machine-level interrupt sources in bits 16 and
123+
above have platform-specific priority, but are typically chosen to have
124+
the highest service priority to support very fast local vectored
125+
interrupts.
126+
127+
External interrupts are handled before internal (timer/software)
128+
interrupts as external interrupts are usually generated by devices that
129+
might require low interrupt service times.
130+
131+
Software interrupts are handled before internal timer interrupts,
132+
because internal timer interrupts are usually intended for time slicing,
133+
where time precision is less important, whereas software interrupts are
134+
used for inter-processor messaging. Software interrupts can be avoided
135+
when high-precision timing is required, or high-precision timer
136+
interrupts can be routed via a different interrupt path. Software
137+
interrupts are located in the lowest four bits of `mip` as these are
138+
often written by software, and this position allows the use of a single
139+
CSR instruction with a five-bit immediate.
140+
====
141+
142+
Restricted views of the `mip` and `mie` registers appear as the `sip`
143+
and `sie` registers for supervisor level. If an interrupt is delegated
144+
to S-mode by setting a bit in the `mideleg` register, it becomes visible
145+
in the `sip` register and is maskable using the `sie` register.
146+
Otherwise, the corresponding bits in `sip` and `sie` are read-only zero.
8147
length: MXLEN
9148
definedBy: Sm
10149
fields:

‎backends/certificate_doc/templates/certificate.adoc.erb‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -559,7 +559,7 @@ h| Privilege Mode | <%= csr.priv_mode %>
559559
|===
560560

561561

562-
==== <%= cert_model.name %> Format
562+
==== Format
563563
<% unless csr.dynamic_length?(arch_def) || csr.implemented_fields(arch_def).any? { |f| f.dynamic_location?(arch_def) } -%>
564564
<%# CSR has a known static length, so there is only one format to display -%>
565565
.<%= csr.name %> format
@@ -587,7 +587,7 @@ This CSR format changes dynamically with XLEN.
587587

588588
<% end # unless dynamic length -%>
589589
590-
==== <%= cert_model.name %> Field Summary
590+
==== Field Summary
591591
592592
// use @ as a separator since IDL code can contain |
593593
[%autowidth,separator=@,float="center",align="center",cols="^,<,<,<",options="header",role="stretch"]
@@ -627,7 +627,7 @@ a@
627627
<%- end -%>
628628
|===
629629
630-
==== <%= cert_model.name %> Fields
630+
==== Fields
631631
632632
<%- if csr.implemented_fields(arch_def).empty? -%>
633633
This CSR has no fields. However, it must still exist (not cause an `Illegal Instruction` trap) and always return zero on a read.

0 commit comments

Comments
 (0)