Merge pull request #257 from riscv-software-src/c_ext

C extension support added

Author: dhower-qc

arch/ext/C.yaml

@@ -3,6 +3,12 @@
 C:
   type: unprivileged
   long_name: Compressed instructions
+  company:
+    name: RISC-V International
+    url: https://riscv.org
+  doc_license:
+    name: Creative Commons Attribution 4.0 International License
+    url: https://creativecommons.org/licenses/by/4.0/
   versions:
   - version: "2.2.0"
     state: ratified

arch/inst/C/c.add.yaml

@@ -0,0 +1,36 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.add:
+  long_name: Add
+  description: |
+    Add the value in rs2 to rd, and store the result in rd.
+    C.ADD expands into `add rd, rd, rs2`. 
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  assembly: xd, rs2
+  encoding:
+    match: 1001----------10
+    variables:
+    - name: rs2
+      location: 6-2
+    - name: rd
+      location: 11-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    XReg t0 = X[rd];
+    XReg t1 = X[rs2];
+    X[rd] = t0 + t1;
+
+  sail(): |
+    {
+      let rs1_val = X(rd);
+      let rs2_val = X(rs2);
+      X(rd) = rs1_val + rs2_val;
+      RETIRE_SUCCESS
+    }

arch/inst/C/c.addi.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.addi:
+  long_name: Add a sign-extended non-zero immediate
+  description: |
+    C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd.
+    C.ADDI expands into `addi rd, rd, imm`. 
+    C.ADDI is only valid when rd≠x0 and imm≠0. 
+    The code points with rd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs.
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  assembly: xd, imm
+  encoding:
+    match: 000-----------01
+    variables:
+    - name: imm
+      location: 12|6-2
+      not: 0
+    - name: rd
+      location: 11-7
+      not: 0
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
+      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+    }
+
+    X[rd] = X[rd] + imm;
+

arch/inst/C/c.addi16sp.yaml

@@ -0,0 +1,33 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.addi16sp:
+  long_name: Add a sign-extended non-zero immediate
+  description: |
+    C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). 
+    C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. 
+    It expands into `addi x2, x2, nzimm[9:4]`. 
+    C.ADDI16SP is only valid when nzimm≠0; the code point with nzimm=0 is reserved.
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  assembly: imm
+  encoding:
+    match: 011-00010-----01
+    variables:
+    - name: imm
+      location: 12|4-3|5|2|6
+      left_shift: 4
+      not: 0
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
+      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+    }
+
+    X[2] = X[2] + imm;
+

arch/inst/C/c.addi4spn.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.addi4spn:
+  long_name: Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer
+  description: |
+    Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd′. 
+    This instruction is used to generate pointers to stack-allocated variables.
+    It expands to `addi rd′, x2, nzuimm[9:2]`. 
+    C.ADDI4SPN is only valid when nzuimm≠0; the code points with nzuimm=0 are reserved.
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  assembly: xd, imm
+  encoding:
+    match: 000-----------00
+    variables:
+    - name: imm
+      location: 10-7|12-11|5|6
+      left_shift: 2
+      not: 0
+    - name: rd
+      location: 4-2
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
+      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+    }
+
+    X[rd+8] = X[2] + imm;
+

arch/inst/C/c.addiw.yaml

@@ -0,0 +1,35 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.addiw:
+  long_name: Add a sign-extended non-zero immediate
+  description: |
+    C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits. 
+    C.ADDIW expands into `addiw rd, rd, imm`. 
+    The immediate can be zero for C.ADDIW, where this corresponds to `sext.w rd`. 
+    C.ADDIW is only valid when rd≠x0; the code points with rd=x0 are reserved.
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  base: 64
+  assembly: xd, imm
+  encoding:
+    match: 001-----------01
+    variables:
+    - name: imm
+      location: 12|6-2
+    - name: rd
+      location: 11-7
+      not: 0
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
+      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+    }
+
+    X[rd] = sext((X[rd] + imm), 32);
+

arch/inst/C/c.addw.yaml

@@ -0,0 +1,45 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.addw:
+  long_name: Add word
+  description: |
+    Add the 32-bit values in rs2 from rd, and store the result in rd.
+    The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
+    C.ADDW expands into `addw rd, rd, rs2`. 
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  base: 64
+  assembly: xd, rs2
+  encoding:
+    match: 100111---01---01
+    variables:
+    - name: rs2
+      location: 4-2
+    - name: rd
+      location: 9-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    Bits<32> t0 = X[rd+8][31:0];
+    Bits<32> t1 = X[rs2+8][31:0];
+    X[rd+8] = sext(t0 + t1, 31);
+
+  sail(): |
+    {
+      let rs1_val = (X(rd+8))[31..0];
+      let rs2_val = (X(rs2+8))[31..0];
+      let result : bits(32) = match op {
+        RISCV_ADDW => rs1_val + rs2_val,
+        RISCV_SUBW => rs1_val - rs2_val,
+        RISCV_SLLW => rs1_val << (rs2_val[4..0]),
+        RISCV_SRLW => rs1_val >> (rs2_val[4..0]),
+        RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0])
+      };
+      X(rd+8) = sign_extend(result);
+      RETIRE_SUCCESS
+    }

arch/inst/C/c.and.yaml

@@ -0,0 +1,55 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.and:
+  long_name: And
+  description: |
+    And rd with rs2, and store the result in rd
+    The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
+    C.AND expands into `and rd, rd, rs2`. 
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  assembly: xd, rs2
+  encoding:
+    match: 100011---11---01
+    variables:
+    - name: rs2
+      location: 4-2
+    - name: rd
+      location: 9-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    XReg t0 = X[rd+8];
+    XReg t1 = X[rs2+8];
+    X[rd+8] = t0 & t1;
+
+  sail(): |
+    {
+      let rs1_val = X(rd+8);
+      let rs2_val = X(rs2+8);
+      let result : xlenbits = match op {
+        RISCV_ADD  => rs1_val + rs2_val,
+        RISCV_SLT  => zero_extend(bool_to_bits(rs1_val <_s rs2_val)),
+        RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)),
+        RISCV_AND  => rs1_val & rs2_val,
+        RISCV_OR   => rs1_val | rs2_val,
+        RISCV_XOR  => rs1_val ^ rs2_val,
+        RISCV_SLL  => if   sizeof(xlen) == 32
+                      then rs1_val << (rs2_val[4..0])
+                      else rs1_val << (rs2_val[5..0]),
+        RISCV_SRL  => if   sizeof(xlen) == 32
+                      then rs1_val >> (rs2_val[4..0])
+                      else rs1_val >> (rs2_val[5..0]),
+        RISCV_SUB  => rs1_val - rs2_val,
+        RISCV_SRA  => if   sizeof(xlen) == 32
+                      then shift_right_arith32(rs1_val, rs2_val[4..0])
+                      else shift_right_arith64(rs1_val, rs2_val[5..0])
+      };
+      X(rd+8) = result;
+      RETIRE_SUCCESS
+    }

arch/inst/C/c.andi.yaml

@@ -0,0 +1,44 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+c.andi:
+  long_name: And immediate
+  description: |
+    And an immediate to the value in rd, and store the result in rd.
+    The rd register index should be used as rd+8 (registers x8-x15).
+    C.ANDI expands into `andi rd, rd, imm`. 
+  definedBy:
+    anyOf:
+    - C
+    - Zca
+  assembly: xd, imm
+  encoding:
+    match: 100-10--------01
+    variables:
+    - name: imm
+      location: 12|6-2
+    - name: rd
+      location: 9-7
+  access:
+    s: always
+    u: always
+    vs: always
+    vu: always
+  operation(): |
+    # shamt is between 0-63
+    X[rd+8] = X[rd+8] & imm;
+
+  sail(): |
+    {
+      let rd_val = X(rd+8);
+      let immext : xlenbits = sign_extend(imm);
+      let result : xlenbits = match op {
+        RISCV_ADDI  => rd_val + immext,
+        RISCV_SLTI  => zero_extend(bool_to_bits(rd_val <_s immext)),
+        RISCV_SLTIU => zero_extend(bool_to_bits(rd_val <_u immext)),
+        RISCV_ANDI  => rd_val & immext,
+        RISCV_ORI   => rd_val | immext,
+        RISCV_XORI  => rd_val ^ immext
+      };
+      X(rd+8) = result;
+      RETIRE_SUCCESS
+    }