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AntonJohanssonAnton Johanssonayosher
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spec: Fix unintentional dead code in branching instructions (#963)
Note: This commit assumes that `jump()` and `jump_halfword()`, which write to `pc` directly, immediately branch upon being executed. And not that branching is implicitly deferred to end of the instruction. Assuming the above, some unditional branch instructions have dead code following a call to `jump()` or `jump_halfword()`. For instance, `qc.e.jal` would not write the return address to `ra`. Signed-off-by: Anton Johansson <[email protected]> Co-authored-by: Anton Johansson <[email protected]> Co-authored-by: ayosher <[email protected]>
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5 files changed

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spec/custom/isa/qc_iu/inst/Xqci/qc.e.jal.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,5 +31,5 @@ access:
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vu: always
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operation(): |
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XReg return_addr = $pc + 6;
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jump_halfword($pc + imm);
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X[1] = return_addr;
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jump_halfword($pc + imm);

spec/std/isa/inst/C/c.jal.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,5 +35,5 @@ operation(): |
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XReg return_addr = $pc + 2;
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jump_halfword($pc + $signed(imm));
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X[1] = return_addr;
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jump_halfword($pc + $signed(imm));

spec/std/isa/inst/C/c.jalr.yaml

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,9 @@ operation(): |
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if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) {
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raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
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}
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XReg addr = X[xs1];
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XReg returnaddr;
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returnaddr = $pc + 2;
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jump(X[xs1]);
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X[1] = returnaddr;
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jump(addr);

spec/std/isa/inst/I/jal.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,8 @@ pseudoinstructions:
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operation(): |
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XReg return_addr = $pc + 4;
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jump_halfword($pc + $signed(imm));
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X[xd] = return_addr;
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jump_halfword($pc + $signed(imm));
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# SPDX-SnippetBegin
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# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/I/jalr.yaml

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,11 +34,12 @@ pseudoinstructions:
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- when: (rd == 0 && xs1 == x1 && imm == 0)
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to: ret
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operation(): |
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XReg addr = (X[xs1] + $signed(imm)) & ~MXLEN'1;
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XReg returnaddr;
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returnaddr = $pc + 4;
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jump((X[xs1] + $signed(imm)) & ~MXLEN'1);
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X[xd] = returnaddr;
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jump(addr);
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# SPDX-SnippetBegin
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# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

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