Merge branch 'main' into dev/kbroch/regex-ratif-date-change

Author: dhower-qc

arch/csr/H/htinst.yaml

@@ -40,5 +40,5 @@ fields:
         return CsrFieldType::RO;
       }
     description: |
-      Exception-speicific information for a trap into HS-mode.
+      Exception-specific information for a trap into HS-mode.
     reset_value: UNDEFINED_LEGAL

arch/csr/H/htval.yaml

@@ -32,5 +32,5 @@ fields:
         return CsrFieldType::RO;
       }
     description: |
-      Exception-speicific information for a trap into M-mode.
+      Exception-specific information for a trap into M-mode.
     reset_value: UNDEFINED_LEGAL

arch/csr/H/mtinst.yaml

@@ -40,5 +40,5 @@ fields:
         return CsrFieldType::RO;
       }
     description: |
-      Exception-speicific information for a trap into M-mode.
+      Exception-specific information for a trap into M-mode.
     reset_value: UNDEFINED_LEGAL

arch/csr/H/mtval2.yaml

@@ -33,5 +33,5 @@ fields:
         return CsrFieldType::RO;
       }
     description: |
-      Exception-speicific information for a trap into M-mode.
+      Exception-specific information for a trap into M-mode.
     reset_value: UNDEFINED_LEGAL

arch/ext/Zcb.yaml

@@ -0,0 +1,42 @@
+# yaml-language-server: $schema=../../schemas/ext_schema.json
+
+$schema: "ext_schema.json#"
+kind: extension
+name: Zcb
+long_name: Simple code-size saving instructions
+description: |
+  Zcb has simple code-size saving instructions which are easy to implement on all CPUs. 
+  All proposed encodings are currently reserved for all architectures, and have no conflicts with any existing extensions.
+  
+  The Zcb extension depends on the Zca extension.
+  
+  As shown on the individual instruction pages, many of the instructions in Zcb depend upon another extension being implemented. 
+  For example, c.mul is only implemented if M or Zmmul is implemented, and c.sext.b is only implemented if Zbb is implemented.
+
+type: unprivileged
+company:
+  name: RISC-V International
+  url: https://riscv.org
+versions:
+- version: "1.0.0"
+  state: ratified
+  ratification_date: 2023-04
+  repositories:
+    - url: https://github.com/riscv/riscv-code-size-reduction
+      branch: main
+  contributors:
+    - name: Tariq Kurd
+    - name: Ibrahim Abu Kharmeh
+    - name: Torbjørn Viem Ness
+    - name: Matteo Perotti
+    - name: Nidal Faour
+    - name: Bill Traynor
+    - name: Rafael Sene 
+    - name: Xinlong Wu
+    - name: sinan
+    - name: Jeremy Bennett
+    - name: Heda Chen 
+    - name: Alasdair Armstrong
+    - name: Graeme Smecher
+    - name: Nicolas Brunie 
+    - name: Jiawei

arch/inst/B/rori.yaml

@@ -12,7 +12,7 @@ definedBy:
 assembly: xd, xs1, shamt
 encoding:
   RV32:
-    match: 0110000----------101-----0110011
+    match: 0110000----------101-----0010011
     variables:
     - name: shamt
       location: 24-20
@@ -21,7 +21,7 @@ encoding:
     - name: rd
       location: 11-7
   RV64:
-    match: 011000-----------101-----0110011
+    match: 011000-----------101-----0010011
     variables:
     - name: shamt
       location: 25-20

arch/inst/V/vloxseg2ei16.v.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: vloxseg2ei16.v
+long_name: No synopsis available.
+description: |
+      No description available.
+definedBy: V
+assembly: vm, vs2, xs1, vd
+encoding:
+  match: 001011-----------101-----0000111
+  variables:
+  - name: vm
+    location: 25-25
+  - name: vs2
+    location: 24-20
+  - name: rs1
+    location: 19-15
+  - name: vd
+    location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |
+      

arch/inst/V/vloxseg2ei32.v.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: vloxseg2ei32.v
+long_name: No synopsis available.
+description: |
+      No description available.
+definedBy: V
+assembly: vm, vs2, xs1, vd
+encoding:
+  match: 001011-----------110-----0000111
+  variables:
+  - name: vm
+    location: 25-25
+  - name: vs2
+    location: 24-20
+  - name: rs1
+    location: 19-15
+  - name: vd
+    location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |
+      

arch/inst/V/vloxseg2ei64.v.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: vloxseg2ei64.v
+long_name: No synopsis available.
+description: |
+      No description available.
+definedBy: V
+assembly: vm, vs2, xs1, vd
+encoding:
+  match: 001011-----------111-----0000111
+  variables:
+  - name: vm
+    location: 25-25
+  - name: vs2
+    location: 24-20
+  - name: rs1
+    location: 19-15
+  - name: vd
+    location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |
+      

arch/inst/V/vloxseg2ei8.v.yaml

@@ -0,0 +1,29 @@
+# yaml-language-server: $schema=../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: vloxseg2ei8.v
+long_name: No synopsis available.
+description: |
+      No description available.
+definedBy: V
+assembly: vm, vs2, xs1, vd
+encoding:
+  match: 001011-----------000-----0000111
+  variables:
+  - name: vm
+    location: 25-25
+  - name: vs2
+    location: 24-20
+  - name: rs1
+    location: 19-15
+  - name: vd
+    location: 11-7
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |
+