Modify the sverilog generator args to nearly match c-header generator

Add regression task for sverilog gen in GH actions

Author: AliAlaa88

.github/workflows/regress.yml

@@ -190,6 +190,17 @@ jobs:
         uses: ./.github/actions/singularity-setup
       - name: Generate c_header code
         run: ./do gen:c_header
+  regress-gen-sverilog:
+    runs-on: ubuntu-latest
+    env:
+      SINGULARITY: 1
+    steps:
+      - name: Clone Github Repo Action
+        uses: actions/checkout@v4
+      - name: singularity setup
+        uses: ./.github/actions/singularity-setup
+      - name: Generate sverilog_header code
+        run: ./do gen:sverilog
   regress-cpp-unit:
     runs-on: ubuntu-latest
     env:

backends/generators/generator.py

@@ -276,14 +276,15 @@ def load_instructions(
 
                         # Process RV64 encoding
                         rv64_match = rv64_encoding.get("match")
+                        rv32_match = rv32_encoding.get("match")
+
                         if rv64_match:
                             instr_dict[name] = {
                                 "match": rv64_match
                             }  # RV64 gets the default name
 
-                        # Process RV32 encoding with a _rv32 suffix
-                        rv32_match = rv32_encoding.get("match")
-                        if rv32_match:
+                        if rv32_match and rv32_match != rv64_match:
+                            # Process RV32 encoding with a _rv32 suffix
                             instr_dict[f"{name}_rv32"] = {"match": rv32_match}
 
                         continue  # Skip the rest of the loop as we've already added the encodings
@@ -441,11 +442,7 @@ def load_csrs(csr_root, enabled_extensions, include_all=False, target_arch="RV64
                 else:
                     addr_int = int(addr_to_use, 0)
 
-                # For BOTH architecture, add suffix to RV32-specific CSRs
-                if target_arch == "BOTH" and base == 32:
-                    csrs[addr_int] = f"{name.upper()}.RV32"
-                else:
-                    csrs[addr_int] = name.upper()
+                csrs[addr_int] = name.upper()
             except Exception as e:
                 logging.error(f"Error parsing address {addr_to_use} in {path}: {e}")
                 address_errors += 1

backends/generators/sverilog/sverilog_generator.py

@@ -27,18 +27,15 @@ def match_to_sverilog_bits(match_str):
     """Convert a match string to SystemVerilog bit pattern."""
     if not match_str:
         logging.error(f"Empty match string encountered.")
-        # return "32'b" + "?" * 32
 
     # For compressed instructions (16-bit), we need to handle them differently.
     # The 16-bit pattern is in the lower 16 bits,
     # with the upper 16 bits as wildcards
     if len(match_str) == 16:
         # Pad with wildcards on the left for 16-bit instructions
         match_str = "?" * 16 + match_str
-    elif len(match_str) < 32:
-        # For other cases, pad on the right
+    elif len(match_str) != 32:
         logging.error(f"Match string length is {len(match_str)}, expected 32 or 16.")
-        # match_str = match_str + "-" * (32 - len(match_str))
 
     # Convert to SystemVerilog format (0, 1, or ?)
     result = match_str.replace("-", "?")
@@ -51,7 +48,7 @@ def generate_sverilog(instructions, csrs, output_file):
     with open(output_file, "w") as f:
         # Write header
         f.write("\n/* Automatically generated by UDB */\n")
-        f.write("package riscv_instr;\n")
+        f.write(f"package {Path(output_file).stem};\n")
 
         # Find the maximum name length for alignment
         max_instr_len = max(
@@ -69,17 +66,11 @@ def generate_sverilog(instructions, csrs, output_file):
             sv_name = format_instruction_name(name)
             # Pad the name for alignment
             padded_name = sv_name.ljust(max_len)
-            # if not name.startswith("v"):
-            #     logging.info(f"Processing instruction: {name}")
-            #     logging.info(f"Formatted instruction: {sv_name}")
-            #     logging.info(f"Padded instruction: {padded_name}")
-
             # Get the match pattern
             if isinstance(encoding, dict) and "match" in encoding:
                 match = encoding["match"]
             else:
-                # If no match field, use all wildcards
-                logging.warning(f"No match field for instruction {name}.")
+                logging.error(f"No match field for instruction {name}.")
 
             sv_bits = match_to_sverilog_bits(match)
             f.write(f"  localparam logic [31:0] {padded_name} = {sv_bits};\n")
@@ -113,29 +104,36 @@ def parse_args():
         default="../../../gen/resolved_spec/_/csr/",
         help="Directory containing CSR YAML files",
     )
+    parser.add_argument(
+        "--ext-dir",
+        default="../../../arch/ext/",
+        help="Directory containing extension YAML files",
+    )
     parser.add_argument(
         "--output",
         default="riscv_decode_package.svh",
         help="Output SystemVerilog file name",
     )
     parser.add_argument(
-        "--extensions",
-        default="A,D,F,I,M,Q,Zba,Zbb,Zbs,S,System,V,Zicsr,Smpmp,Sm,H,U,Zicntr,Zihpm,Smhpm",
-        help="Comma-separated list of enabled extensions. Default includes standard extensions.",
+        "--include-all",
+        action="store_true",
+        help="Include all instructions and CSRs regardless of extensions",
     )
     parser.add_argument(
-        "--arch",
-        default="RV64",
-        choices=["RV32", "RV64", "BOTH"],
-        help="Target architecture (RV32, RV64, or BOTH). Default is RV64.",
+        "--verbose", "-v", action="store_true", help="Enable verbose logging"
     )
     parser.add_argument(
-        "--verbose", "-v", action="store_true", help="Enable verbose logging"
+        "--extensions",
+        "-e",
+        nargs="+",
+        default=[],
+        help="Comma-separated list of enabled extensions.",
     )
     parser.add_argument(
-        "--include-all",
-        action="store_true",
-        help="Include all instructions and CSRs regardless of extensions",
+        "--arch",
+        default="BOTH",
+        choices=["RV32", "RV64", "BOTH"],
+        help="Target architecture (RV32, RV64, or BOTH). Default is RV64.",
     )
     return parser.parse_args()
 
@@ -167,6 +165,8 @@ def main():
     csrs = load_csrs(args.csr_dir, enabled_extensions, args.include_all, args.arch)
     logging.info(f"Loaded {len(csrs)} CSRs")
 
+    # Todo: Load exception codes here
+
     # Generate the SystemVerilog file
     generate_sverilog(instructions, csrs, args.output)
     logging.info(

backends/generators/tasks.rake

@@ -108,8 +108,9 @@ namespace :gen do
     cfg_arch = resolver.cfg_arch_for(config_name)
     inst_dir = cfg_arch.path / "inst"
     csr_dir = cfg_arch.path / "csr"
+    ext_dir = cfg_arch.path / "ext"
 
     # Run the SystemVerilog generator script using the same Python environment
-    sh "#{$root}/.home/.venv/bin/python3 #{$root}/backends/generators/sverilog/sverilog_generator.py --inst-dir=#{inst_dir} --csr-dir=#{csr_dir} --output=#{output_dir}riscv_decode_package.svh"
+    sh "#{$root}/.home/.venv/bin/python3 #{$root}/backends/generators/sverilog/sverilog_generator.py --inst-dir=#{inst_dir} --csr-dir=#{csr_dir} --ext-dir=#{ext_dir} --output=#{output_dir}riscv_decode_package.svh --include-all"
   end
 end