fix: correcting handling of fence.i

Author: henrikg-qc

backends/cpp_hart_gen/cpp/include/udb/bits.hpp

@@ -2976,7 +2976,31 @@ namespace udb {
       }
     }
 
-    void apply_mask() { m_val = m_val & _RuntimeBits<MaxN, false>{mask(), m_width}; }
+    bool needs_mask() const {
+      if constexpr (MaxN > BitsMaxNativePrecision) {
+        if (m_width == BitsInfinitePrecision) {
+          // special case: we store infinite numbers with their sign
+          return false;
+        } else {
+          // gmp storage, without upper bound, so everything needs masked
+          return true;
+        }
+      } else {
+        if (m_width == (sizeof(StorageType) * 8)) {
+          // we fit exactly in our native storage
+          return false;
+        } else {
+          // using native storage, but there are unused bits
+          return true;
+        }
+      }
+    }
+
+    void apply_mask() {
+      if(needs_mask()) {
+        m_val = m_val & _RuntimeBits<MaxN, false>{mask(), m_width};
+      }
+    }
 
    public:
     // used for template concept resolution

backends/cpp_hart_gen/cpp/include/udb/hart.hpp

@@ -169,7 +169,8 @@ namespace udb {
       m_soc.fence(pi, pr, po, pw, si, sr, so, sw);
     }
     void fence_tso() { m_soc.fence_tso(); }
-    void ifence() { m_soc.ifence(); }
+    virtual void ifence() { m_soc.ifence(); }
+
     template <typename... Args>
     void order_pgtbl_writes_before_vmafence(Args...) {
       // TODO: pass along order info (not easy now because VmaOrderType is

backends/cpp_hart_gen/templates/hart.hxx.erb

@@ -464,6 +464,11 @@ namespace udb {
 
     uint64_t fetch() override { return _fetch().get(); }
     PossiblyUnknownBits<INSTR_ENC_SIZE.get()> _fetch();
+    void ifence() override {
+      m_bb_cache.invalidate();
+      HartBase<SocType>::ifence();
+      this->m_exit_requested = true;
+    }
 
     <%= name_of(:struct, cfg_arch, "CachedTranslationResult") %> cached_translation(const PossiblyUnknownBits<64>& vaddr, const MemoryOperation& op) const {
       <%- if cfg_arch.symtab.get("CachedTranslationResult").runtime? -%>

backends/cpp_hart_gen/templates/hart_impl.hxx.erb

@@ -142,11 +142,12 @@ namespace udb {
           m_next_pc = m_pc + Bits<MXLEN>{inst->enc_len()};
 
           inst->execute();
+
+          advance_pc();
           if (this->m_exit_requested) {
-            this->m_exit_requested = false; // reset the request
+            this->m_exit_requested = false;  // reset the request
             break;
           }
-          advance_pc();
         }
       } else {
         // miss, need to create the bb
@@ -174,12 +175,11 @@ namespace udb {
             fmt::print("R= {} {:x}\n", r.to_string(), _xreg(r.get_num()));
           }
 
+          advance_pc();
           if (this->m_exit_requested) {
             this->m_exit_requested = false; // reset the request
             break;
           }
-
-          advance_pc();
         } while (!(current_bb->full() || inst->control_flow()));
       }
     } catch (const AbortInstruction& e) {

cfgs/mc100-32-riscv-tests.yaml

@@ -3,7 +3,7 @@
 $schema: https://riscv.org/udb/schemas/config_schema-0.1.0.json
 kind: architecture configuration
 type: fully configured
-name: MC100-32-Full
+name: MC100-32-riscv-tests
 description: An example MC100-32-compliant full config for riscv-tests
 implemented_extensions:
   - [Sm, "1.11.0"]
@@ -16,6 +16,7 @@ implemented_extensions:
   - [S, "1.11.0"]
   - [Smpmp, "1.11.0"]
   - [U, "1.0.0"]
+  - [Zifencei, "2.0.0"]
 
 params:
   MXLEN: 32