fix(Xqci): xqciv0p13 changes

Xqci/Xqcicsr - add missing code and description in qc.csrrwr instruction

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

arch_overlay/qc_iu/ext/Xqci.yaml

@@ -379,13 +379,13 @@ versions:
   - { name: Xqcicm, version: "0.2.0" }
   - { name: Xqcics, version: "0.2.0" }
   - { name: Xqcicsr, version: "0.3.0" }
-  - { name: Xqciint, version: "0.8.0" }
+  - { name: Xqciint, version: "0.9.0" }
   - { name: Xqciio, version: "0.1.0" }
   - { name: Xqcilb, version: "0.2.0" }
   - { name: Xqcili, version: "0.2.0" }
   - { name: Xqcilia, version: "0.2.0" }
   - { name: Xqcilo, version: "0.3.0" }
-  - { name: Xqcilsm, version: "0.6.0" }
+  - { name: Xqcilsm, version: "0.5.0" }
   - { name: Xqcisim, version: "0.2.0" }
   - { name: Xqcisls, version: "0.2.0" }
   - { name: Xqcisync, version: "0.3.0" }
@@ -421,7 +421,42 @@ versions:
   - { name: Xqcili, version: "0.2.0" }
   - { name: Xqcilia, version: "0.2.0" }
   - { name: Xqcilo, version: "0.3.0" }
-  - { name: Xqcilsm, version: "0.5.0" }
+  - { name: Xqcilsm, version: "0.6.0" }
+  - { name: Xqcisim, version: "0.2.0" }
+  - { name: Xqcisls, version: "0.2.0" }
+  - { name: Xqcisync, version: "0.3.0" }
+  requires:
+    name: Zca
+    version: ">= 1.0.0"
+- version: "0.13.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix version history of releases v0.11.0 and v0.12.0
+    - Fix description and IDL code of qc.csrrwr instruction to allow just read CSR
+  implies:
+  - { name: Xqcia, version: "0.7.0" }
+  - { name: Xqciac, version: "0.3.0" }
+  - { name: Xqcibi, version: "0.2.0" }
+  - { name: Xqcibm, version: "0.8.0" }
+  - { name: Xqcicli, version: "0.3.0" }
+  - { name: Xqcicm, version: "0.2.0" }
+  - { name: Xqcics, version: "0.2.0" }
+  - { name: Xqcicsr, version: "0.4.0" }
+  - { name: Xqciint, version: "0.9.0" }
+  - { name: Xqciio, version: "0.1.0" }
+  - { name: Xqcilb, version: "0.2.0" }
+  - { name: Xqcili, version: "0.2.0" }
+  - { name: Xqcilia, version: "0.2.0" }
+  - { name: Xqcilo, version: "0.3.0" }
+  - { name: Xqcilsm, version: "0.6.0" }
   - { name: Xqcisim, version: "0.2.0" }
   - { name: Xqcisls, version: "0.2.0" }
   - { name: Xqcisync, version: "0.3.0" }

arch_overlay/qc_iu/ext/Xqcicsr.yaml

@@ -40,6 +40,18 @@ versions:
     email: [email protected]
   changes:
     - Remove qc.flags CSR
+- version: "0.4.0"
+  state: frozen
+  ratification_date: null
+  contributors:
+  - name: Albert Yosher
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  - name: Derek Hower
+    company: Qualcomm Technologies, Inc.
+    email: [email protected]
+  changes:
+    - Fix description and IDL code of qc.csrrwr instruction to allow just read CSR
 description: |
   The Xqcicsr extension contains two instructions to read/write CSR which index is in register and not immediate.
 

arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml

@@ -12,6 +12,8 @@ description: |
   The initial value in `rs1` is written to the CSR.
   If `rd`=`x0`, then the instruction shall not read the CSR and shall not
   cause any of the side effects that might occur on a CSR read.
+  If `rs1`=`x0`, then the instruction shall not write to the CSR and shall not
+  cause any of the side effects that might occur on a CSR write.
   Instruction encoded in R instruction format.
 definedBy:
   anyOf:
@@ -40,6 +42,8 @@ operation(): |
   if (rd != 0) {
     X[rd] = csr_sw_read(csr);
   }
-  # writes the value in X[rs1] to the CSR,
-  # performing any WARL transformations first
-  csr_sw_write(csr, X[rs1]);
+  if (rs1 != 0) {
+    # writes the value in X[rs1] to the CSR,
+    # performing any WARL transformations first
+    csr_sw_write(csr, X[rs1]);
+  }