Update backends/generators/sverilog/sverilog_generator.py

Co-authored-by: Jordan Carlin <[email protected]>
Signed-off-by: Alieldin Alaa <[email protected]>

Author: AliAlaa88

backends/generators/sverilog/sverilog_generator.py

@@ -52,7 +52,7 @@ def generate_sverilog(instructions, csrs, causes, output_file):
     """Generate SystemVerilog package file."""
     with open(output_file, "w") as f:
         # Write header
-        f.write("\n/* Automatically generated by UDB */\n")
+        f.write("/* Automatically generated by UDB */\n")
         f.write(f"package {Path(output_file).stem};\n")
 
         # Find the maximum name length for alignment