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1 parent 90e0334 commit 7a8c572Copy full SHA for 7a8c572
spec/std/isa/inst/Zicsr/csrrs.yaml
@@ -33,6 +33,24 @@ access:
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vs: always
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vu: always
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pseudoinstructions:
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+ - when: xs1 == 0 && csr == 0x001
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+ to: frflags xd
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+ - when: xs1 == 0 && csr == 0x002
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+ to: frrm xd
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+ - when: xs1 == 0 && csr == 0x003
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+ to: frcsr xd
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+ - when: xs1 == 0 && csr == 0xC00
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+ to: rdcycle xd
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+ - when: xs1 == 0 && csr == 0xC01
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+ to: rdtime xd
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+ - when: xs1 == 0 && csr == 0xC02
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+ to: rdinstret xd
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+ - when: xs1 == 0 && csr == 0xC80
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+ to: rdcycleh xd
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+ - when: xs1 == 0 && csr == 0xC81
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+ to: rdtimeh xd
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+ - when: xs1 == 0 && csr == 0xC82
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+ to: rdinstreth xd
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- when: xs1 == 0
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to: csrr xd,csr
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- when: xd == 0
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