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12 files changed

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‎spec/std/isa/csr/cycle.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ sw_read(): |
4545
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
4646
}
4747
} else if (mode() == PrivilegeMode::U) {
48-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b1))) {
48+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || CSR[misa].S == 1'b1) {
4949
# S-mode is present ->
5050
# mcounteren and scounteren together determine access in U-mode
5151
if ((CSR[mcounteren].CY & CSR[scounteren].CY) == 1'b0) {

‎spec/std/isa/csr/mip.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -411,6 +411,6 @@ sw_read(): |
411411
# OR in the hidden smode external interrupt
412412
return
413413
$bits(CSR[mip])
414-
| (((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b1 ))&& pending_smode_external_interrupt)
414+
| (((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b1)) && pending_smode_external_interrupt
415415
? 10'h200
416416
: 0);

‎spec/std/isa/csr/misa.yaml‎

Lines changed: 35 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,8 @@ fields:
3737
[when,"MUTABLE_MISA_A == true"]
3838
Writing 0 to this field will cause all atomic instructions to raise an `IllegalInstruction` exception.
3939
type(): |
40-
if (MISA_CSR_IMPLEMENTED) {
41-
return (implemented?(ExtensionName::A) && MUTABLE_MISA_A) ? CsrFieldType::RW : CsrFieldType::RO;
40+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::A) && MUTABLE_MISA_A) {
41+
return CsrFieldType::RW;
4242
} else {
4343
return CsrFieldType::RO;
4444
}
@@ -57,8 +57,8 @@ fields:
5757
[when,"MUTABLE_MISA_B == true"]
5858
Writing 0 to this field will cause all bitmanip instructions to raise an `IllegalInstruction` exception.
5959
type(): |
60-
if (MISA_CSR_IMPLEMENTED) {
61-
return (implemented?(ExtensionName::B) && MUTABLE_MISA_B) ? CsrFieldType::RW : CsrFieldType::RO;
60+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::B) && MUTABLE_MISA_B) {
61+
return CsrFieldType::RW;
6262
} else {
6363
return CsrFieldType::RO;
6464
}
@@ -78,8 +78,8 @@ fields:
7878
Writing 0 to this field will cause all compressed instructions to raise an `IllegalInstruction` exception.
7979
Additionally, IALIGN becomes 32.
8080
type(): |
81-
if (MISA_CSR_IMPLEMENTED) {
82-
return (implemented?(ExtensionName::C) && MUTABLE_MISA_C) ? CsrFieldType::RW : CsrFieldType::RO;
81+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::C) && MUTABLE_MISA_C) {
82+
return CsrFieldType::RW;
8383
} else {
8484
return CsrFieldType::RO;
8585
}
@@ -102,8 +102,8 @@ fields:
102102
Additionally, the upper 32-bits of the f registers will read as zero.
103103
--
104104
type(): |
105-
if (MISA_CSR_IMPLEMENTED) {
106-
return (implemented?(ExtensionName::D) && MUTABLE_MISA_D) ? CsrFieldType::RW : CsrFieldType::RO;
105+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::D) && MUTABLE_MISA_D) {
106+
return CsrFieldType::RW;
107107
} else {
108108
return CsrFieldType::RO;
109109
}
@@ -126,8 +126,8 @@ fields:
126126
Writing 0 to this field with `misa.D` set will result in UNDEFINED behavior.
127127
--
128128
type(): |
129-
if (MISA_CSR_IMPLEMENTED) {
130-
return (implemented?(ExtensionName::F) && MUTABLE_MISA_F) ? CsrFieldType::RW : CsrFieldType::RO;
129+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::F) && MUTABLE_MISA_F) {
130+
return CsrFieldType::RW;
131131
} else {
132132
return CsrFieldType::RO;
133133
}
@@ -190,8 +190,8 @@ fields:
190190
[when,"MUTABLE_MISA_H == true"]
191191
Writing 0 to this field will cause all attempts to enter VS- or VU- mode, execute a hypervisor instruction, or access a hypervisor CSR to raise an `IllegalInstruction` fault.
192192
type(): |
193-
if (MISA_CSR_IMPLEMENTED) {
194-
return (implemented?(ExtensionName::H) && MUTABLE_MISA_H) ? CsrFieldType::RW : CsrFieldType::RO;
193+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::H) && MUTABLE_MISA_H) {
194+
return CsrFieldType::RW;
195195
} else {
196196
return CsrFieldType::RO;
197197
}
@@ -209,11 +209,7 @@ fields:
209209
type: RO
210210
definedBy: I
211211
reset_value(): |
212-
if (MISA_CSR_IMPLEMENTED) {
213-
return 1;
214-
} else {
215-
return 0;
216-
}
212+
return MISA_CSR_IMPLEMENTED ? 1 : 0;
217213
M:
218214
location: 12
219215
description: |
@@ -273,11 +269,7 @@ fields:
273269
return CsrFieldType::RO;
274270
}
275271
reset_value(): |
276-
if (MISA_CSR_IMPLEMENTED) {
277-
return 1;
278-
} else {
279-
return 0;
280-
}
272+
return MISA_CSR_IMPLEMENTED ? 1 : 0;
281273
definedBy: Q
282274
sw_write(csr_value): |
283275
if (MISA_CSR_IMPLEMENTED) {
@@ -304,8 +296,8 @@ fields:
304296
[when,"MUTABLE_MISA_S == true"]
305297
Writing 0 to this field will cause all attempts to enter S-mode or access S-mode state to raise an exception.
306298
type(): |
307-
if (MISA_CSR_IMPLEMENTED) {
308-
return (implemented?(ExtensionName::S) && MUTABLE_MISA_S) ? CsrFieldType::RW : CsrFieldType::RO;
299+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S) && MUTABLE_MISA_S) {
300+
return CsrFieldType::RW;
309301
} else {
310302
return CsrFieldType::RO;
311303
}
@@ -324,8 +316,8 @@ fields:
324316
[when,"MUTABLE_MISA_U == true"]
325317
Writing 0 to this field will cause all attempts to enter U-mode to raise an exception.
326318
type(): |
327-
if (MISA_CSR_IMPLEMENTED) {
328-
return (implemented?(ExtensionName::U) && MUTABLE_MISA_U) ? CsrFieldType::RW : CsrFieldType::RO;
319+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::U) && MUTABLE_MISA_U) {
320+
return CsrFieldType::RW;
329321
} else {
330322
return CsrFieldType::RO;
331323
}
@@ -347,8 +339,8 @@ fields:
347339
[when,"MISA_CSR_IMPLEMENTED == false"]
348340
This field reads as 0 and cannot be modified.
349341
type(): |
350-
if (MISA_CSR_IMPLEMENTED) {
351-
return (implemented?(ExtensionName::V) && MUTABLE_MISA_V) ? CsrFieldType::RW : CsrFieldType::RO;
342+
if (MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::V) && MUTABLE_MISA_V) {
343+
return CsrFieldType::RW;
352344
} else {
353345
return CsrFieldType::RO;
354346
}
@@ -360,24 +352,23 @@ fields:
360352
}
361353
definedBy: V
362354
sw_read(): |
363-
if (MISA_CSR_IMPLEMENTED) {
364-
return (
365-
(CSR[misa].MXL << (xlen() - 2)) |
366-
(CSR[misa].V << 21) |
367-
(CSR[misa].U << 20) |
368-
(CSR[misa].S << 18) |
369-
(CSR[misa].M << 12) |
370-
(CSR[misa].I << 8) |
371-
(CSR[misa].H << 7) |
372-
((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) << 6) | # 'G'
373-
(CSR[misa].F << 5) |
374-
(CSR[misa].D << 3) |
375-
(CSR[misa].C << 2) |
376-
(CSR[misa].B << 1) |
377-
CSR[misa].A);
378-
} else {
355+
if (!MISA_CSR_IMPLEMENTED) {
379356
return 0;
380357
}
358+
return (
359+
(CSR[misa].MXL << (xlen() - 2)) |
360+
(CSR[misa].V << 21) |
361+
(CSR[misa].U << 20) |
362+
(CSR[misa].S << 18) |
363+
(CSR[misa].M << 12) |
364+
(CSR[misa].I << 8) |
365+
(CSR[misa].H << 7) |
366+
((CSR[misa].A & CSR[misa].M & CSR[misa].F & CSR[misa].D) << 6) | # 'G'
367+
(CSR[misa].F << 5) |
368+
(CSR[misa].D << 3) |
369+
(CSR[misa].C << 2) |
370+
(CSR[misa].B << 1) |
371+
CSR[misa].A);
381372
cert_normative_rules:
382373
- id: csr.misa.disabling_bits
383374
name: Disabling `misa` bits

‎spec/std/isa/csr/mstatus.yaml‎

Lines changed: 26 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -282,22 +282,22 @@ fields:
282282
* Any additional traps in VS-mode (controlled via `hstatus.VTVM` instead).
283283
284284
type(): |
285-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) {
285+
if ((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) {
286286
return CsrFieldType::RO;
287287
} else {
288288
return CsrFieldType::RW;
289289
}
290290
definedBy: S
291291
reset_value(): |
292-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) {
292+
if ((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) {
293293
return 0;
294294
} else if (MSTATUS_TVM_IMPLEMENTED) {
295295
return UNDEFINED_LEGAL;
296296
} else {
297297
return 0;
298298
}
299299
sw_write(csr_value): |
300-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) {
300+
if ((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) {
301301
return 0;
302302
} else if (MSTATUS_TVM_IMPLEMENTED) {
303303
return csr_value.TVM;
@@ -347,7 +347,7 @@ fields:
347347
`mstatus.MPRV` is cleared on any exception return (`mret` or `sret` instruction, regardless of the trap handler privilege mode).
348348
definedBy: U
349349
type(): |
350-
return ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].U == 1'b1))) ? CsrFieldType::RWH : CsrFieldType::RO;
350+
return ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::U)) || (CSR[misa].U == 1'b1)) ? CsrFieldType::RWH : CsrFieldType::RO;
351351
reset_value: 0
352352
XS:
353353
location: 16-15
@@ -370,9 +370,10 @@ fields:
370370
Values 1 and 2 are valid write values for software, but are not interpreted by hardware
371371
other than to possibly enable a previously-disabled floating point unit.
372372
type(): |
373-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].F == 1'b1))){
373+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::F)) || (CSR[misa].F == 1'b1)) {
374374
return CsrFieldType::RWH;
375-
} else if (((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) && ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].F == 1'b0)))) {
375+
} else if (((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) &&
376+
((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::F)) || (CSR[misa].F == 1'b0))) {
376377
# must be read-only-0
377378
return CsrFieldType::RO;
378379
} else {
@@ -382,19 +383,21 @@ fields:
382383
definedBy:
383384
anyOf: [F, S]
384385
reset_value(): |
385-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].F == 1'b1))){
386+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::F)) || (CSR[misa].F == 1'b1)) {
386387
return UNDEFINED_LEGAL;
387-
} else if (((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) && ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].F == 1'b0)))) {
388+
} else if (((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) &&
389+
((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::F)) || (CSR[misa].F == 1'b0))) {
388390
# must be read-only-0
389391
return 0;
390392
} else {
391393
# there will be no hardware update in this case because we know the F extension isn't implemented
392394
return MSTATUS_FS_WRITABLE ? UNDEFINED_LEGAL : 0;
393395
}
394396
sw_write(csr_value): |
395-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].F == 1'b1))){
397+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::F)) || (CSR[misa].F == 1'b1)) {
396398
return ary_includes?<$array_size(MSTATUS_FS_LEGAL_VALUES), 2>(MSTATUS_FS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
397-
} else if (((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) && ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].F == 1'b0)))) {
399+
} else if (((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) &&
400+
((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::F)) || (CSR[misa].F == 1'b0))) {
398401
# must be read-only-0
399402
return 0;
400403
} else {
@@ -454,29 +457,32 @@ fields:
454457
definedBy:
455458
anyOf: [V, S]
456459
type(): |
457-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].V == 1'b1))){
460+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::V)) || (CSR[misa].V == 1'b1)) {
458461
return CsrFieldType::RWH;
459-
} else if (((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) && ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].V == 1'b0)))) {
462+
} else if (((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) &&
463+
((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::V)) || (CSR[misa].V == 1'b0))) {
460464
# must be read-only-0
461465
return CsrFieldType::RO;
462466
} else {
463467
# there will be no hardware update in this case because we know the V extension isn't implemented
464468
return MSTATUS_VS_WRITABLE ? CsrFieldType::RW : CsrFieldType::RO;
465469
}
466470
reset_value(): |
467-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].V == 1'b1))){
471+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::V)) || (CSR[misa].V == 1'b1)) {
468472
return UNDEFINED_LEGAL;
469-
} else if (((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) && ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].V == 1'b0)))) {
473+
} else if (((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) &&
474+
((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::V)) || (CSR[misa].V == 1'b0))) {
470475
# must be read-only-0
471476
return 0;
472477
} else {
473478
# there will be no hardware update in this case because we know the V extension isn't implemented
474479
return MSTATUS_VS_WRITABLE ? UNDEFINED_LEGAL : 0;
475480
}
476481
sw_write(csr_value): |
477-
if ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].V == 1'b1))){
482+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::V)) || (CSR[misa].V == 1'b1)) {
478483
return ary_includes?<$array_size(MSTATUS_VS_LEGAL_VALUES), 2>(MSTATUS_VS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
479-
} else if (((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b0))) && ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].V == 1'b0)))) {
484+
} else if (((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b0)) &&
485+
((!MISA_CSR_IMPLEMENTED && !implemented?(ExtensionName::V)) || (CSR[misa].V == 1'b0))) {
480486
# must be read-only-0
481487
return 0;
482488
} else {
@@ -569,10 +575,10 @@ fields:
569575
570576
Other than serving as a record of nested traps as described above, `mstatus.SPIE` does not affect execution.
571577
type(): |
572-
return ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b1))) ? CsrFieldType::RWH : CsrFieldType::RO;
578+
return ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b1)) ? CsrFieldType::RWH : CsrFieldType::RO;
573579
definedBy: S
574580
reset_value(): |
575-
return ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b1))) ? UNDEFINED_LEGAL : 0;
581+
return ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b1)) ? UNDEFINED_LEGAL : 0;
576582
MIE:
577583
location: 3
578584
description: |
@@ -606,7 +612,7 @@ fields:
606612
* When 1, (H)S-mode interrupts that are not otherwise disabled with a field in `sie` are enabled.
607613
608614
type(): |
609-
return ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b1))) ? CsrFieldType::RWH : CsrFieldType::RO;
615+
return ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b1)) ? CsrFieldType::RWH : CsrFieldType::RO;
610616
definedBy: S
611617
reset_value(): |
612-
return ((!MISA_CSR_IMPLEMENTED) || ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1'b1))) ? UNDEFINED_LEGAL : 0;
618+
return ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || (CSR[misa].S == 1'b1)) ? UNDEFINED_LEGAL : 0;

‎spec/std/isa/ext/Sm.yaml‎

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -456,15 +456,7 @@ params:
456456
schema:
457457
type: boolean
458458
default: true
459-
MISA_READ_ONLY_ZERO:
460-
description: |
461-
When true, indicates the `misa` CSR is hardwired to read-only zero.
462-
When false, the `misa` CSR behaves as a standard WARL register.
463-
Only applicable when MISA_CSR_IMPLEMENTED == false.
464-
schema:
465-
type: boolean
466-
default: false
467-
MTVEC_MODES:
459+
MTVEC_MODES:
468460
description: |
469461
Modes supported by `mtvec.MODE`. If only one, it is assumed to be read-only with that value.
470462
schema:

‎spec/std/isa/ext/Zhinx.yaml‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,23 @@
11
# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
22
# SPDX-License-Identifier: BSD-3-Clause-Clear
33

4-
# yaml-language-server: $schema=../../schemas/ext_schema.json
5-
6-
$schema: "ext_schema.json#"
7-
kind: extension
8-
name: Zhinx
9-
long_name: Half-precision floating-point instructions using integer registers
10-
description: |
11-
The Zhinx extension provides analogous half-precision floating-point instructions. The Zhinx extension
12-
depends upon the Zfinx extension.
13-
The Zhinx extension adds all of the instructions that the Zfh extension adds, except for the transfer
14-
instructions FLH, FSH, FMV.H.X, and FMV.X.H.
15-
The Zhinx variants of these Zfh-extension instructions have the same semantics, except that whenever
16-
such an instruction would have accessed an f register, it instead accesses the x register with the same
17-
number.
18-
19-
type: unprivileged
20-
versions:
21-
- version: "1.0.0"
22-
state: ratified
23-
ratification_date: 2021-11
4+
# yaml-language-server: $schema=../../schemas/ext_schema.json
5+
6+
$schema: "ext_schema.json#"
7+
kind: extension
8+
name: Zhinx
9+
long_name: Half-precision floating-point instructions using integer registers
10+
description: |
11+
The Zhinx extension provides analogous half-precision floating-point instructions. The Zhinx extension
12+
depends upon the Zfinx extension.
13+
The Zhinx extension adds all of the instructions that the Zfh extension adds, except for the transfer
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instructions FLH, FSH, FMV.H.X, and FMV.X.H.
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The Zhinx variants of these Zfh-extension instructions have the same semantics, except that whenever
16+
such an instruction would have accessed an f register, it instead accesses the x register with the same
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number.
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19+
type: unprivileged
20+
versions:
21+
- version: "1.0.0"
22+
state: ratified
23+
ratification_date: 2021-11

‎spec/std/isa/isa/fetch.idl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ function fetch_memory_aligned_16 {
1313
body {
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TranslationResult result;
1515

16-
if ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1)) {
16+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || (CSR[misa].S == 1)) {
1717
result = translate(virtual_address, MemoryOperation::Fetch, mode(), virtual_address);
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} else {
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result.paddr = virtual_address;
@@ -36,7 +36,7 @@ function fetch_memory_aligned_32 {
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body {
3737
TranslationResult result;
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39-
if ((!MISA_CSR_IMPLEMENTED) || (CSR[misa].S == 1)) {
39+
if ((!MISA_CSR_IMPLEMENTED && implemented?(ExtensionName::S)) || (CSR[misa].S == 1)) {
4040
result = translate(virtual_address, MemoryOperation::Fetch, mode(), virtual_address);
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} else {
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result.paddr = virtual_address;

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