Merge branch '1222-add-rvi20-crds-to-those-built-and-published-as-artifacts' of https://github.com/riscv-software-src/riscv-unified-db into 1222-add-rvi20-crds-to-those-built-and-published-as-artifacts

Author: james-ball-qualcomm

bin/setup

@@ -130,9 +130,9 @@ elif [ "${CONTAINER_TYPE}" == "docker" -o "${CONTAINER_TYPE}" == "podman" ]; the
       SELINUX_LABEL=""
     fi
     if [ -t 1 -a -t 0 ]; then
-      CONTAINER_BASE="${CONTAINER_TYPE} run -it -v ${ROOT}:${ROOT}${SELINUX_LABEL} -w ${ROOT} riscvintl/udb:${CONTAINER_TAG}"
+      CONTAINER_BASE="${CONTAINER_TYPE} run --rm -it -v ${ROOT}:${ROOT}${SELINUX_LABEL} -w ${ROOT} riscvintl/udb:${CONTAINER_TAG}"
     else
-      CONTAINER_BASE="${CONTAINER_TYPE} run -v ${ROOT}:${ROOT}${SELINUX_LABEL} -w ${ROOT} riscvintl/udb:${CONTAINER_TAG}"
+      CONTAINER_BASE="${CONTAINER_TYPE} run --rm -v ${ROOT}:${ROOT}${SELINUX_LABEL} -w ${ROOT} riscvintl/udb:${CONTAINER_TAG}"
     fi
 elif [ "${CONTAINER_TYPE}" == "singularity" ]; then
     CONTAINER_PATH=${ROOT}/.singularity/image-$CONTAINER_TAG.sif

package-lock.json

@@ -23,12 +23,10 @@ in_scope_priv_modes:
 # History of this certificate.
 revision_history:
   - revision: "0.9.0"
-    date: "2025-02-06"
+    date: "2025-10-29"
     changes:
       - |
-        Provided to CSC Microcontroller WG for review given the following list of known issues:
-          ** abc
-          ** def
+        Made Zicntr from mandatory to optional since recent published ISA manuals have it as "recommended"
   - revision: "0.8.0"
     date: "2025-01-19"
     changes:
@@ -118,7 +116,7 @@ extensions:
     presence: mandatory
   Zicntr:
     version: "~> 2.0"
-    presence: mandatory
+    presence: optional
     param_constraints:
       TIME_CSR_IMPLEMENTED: {} # Unconstrained
   Sm:

spec/std/isa/proc_cert_model/MC100-32.yaml

@@ -46,6 +46,8 @@ debug_manual_revision: "0.13.2"
 # TODO: No ratified CLIC yet. It will be multiple extensions.
 
 extensions:
+  Zicntr:
+    presence: mandatory
   M:
     presence: mandatory
   B: