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Derek Hower
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Change cert model schema
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‎Rakefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -287,7 +287,7 @@ task :regress do
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ENV["VERSIONS"] = "all"
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Rake::Task["gen:html_manual"].invoke
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Rake::Task["gen:html"].invoke("generic_rv64")
290-
Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel.pdf"].invoke
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Rake::Task["#{$root}/gen/certificate_doc/pdf/MockCertificateModel100.pdf"].invoke
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Rake::Task["#{$root}/gen/certificate_doc/pdf/MC100.pdf"].invoke
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Rake::Task["#{$root}/gen/profile_doc/pdf/MockProfileRelease.pdf"].invoke
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Rake::Task["#{$root}/gen/profile_doc/pdf/RVA20.pdf"].invoke

‎arch/certificate_model/MC100.yaml‎

Lines changed: 132 additions & 130 deletions
Original file line numberDiff line numberDiff line change
@@ -1,141 +1,143 @@
1-
# yaml-language-server: $schema=../../schemas/testplan_schema.json
1+
# yaml-language-server: $schema=../../schemas/cert_model_schema.json
22

3-
MC100:
4-
name: MC100
5-
long_name: Basic Microcontroller Certificate
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class: MC
7-
model: 100
3+
$schema: cert_model_schema.json#
4+
kind: certificate model
5+
name: MC100
6+
long_name: Basic Microcontroller Certificate
7+
class:
8+
$ref: certificate_class/MC.yaml#
9+
model: 100
810

9-
# Semantic versions within the model
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versions:
11-
- version: "1.0.0"
11+
# Semantic versions within the model
12+
versions:
13+
- version: "1.0.0"
1214

13-
# XLEN used by rakefile
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base: 32
15+
# XLEN used by rakefile
16+
base: 32
1517

16-
revision_history:
17-
- revision: "0.7"
18-
date: 2024-07-29
19-
changes:
20-
- First version after moving non-microcontroller content in this document to a new document
21-
called "RISC-V CRDs (Certification Requirement Documents)"
22-
- Change MC100 Unpriv ISA spec from
23-
"https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
24-
2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
25-
former isn't ratified by the latter is the oldest ratified version.
26-
- Added requirements for WFI instruction
27-
- Added requirements related to msip memory-mapped register
28-
- revision: "0.6"
29-
date: 2024-07-11
30-
changes:
31-
- Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
32-
- Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
33-
- Added a table showing the mapping from MC version to ISA manuals.
34-
- Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller
35-
was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations.
36-
- Clarified MANDATORY behaviors for mie and mip CSRs
37-
- Removed canonical discovery recipe because the OPT-* options directly inform the certification
38-
tests and certification reference model of the status of the various options. Also, canonical
39-
discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
40-
potentially illegal values to CSR fields.
41-
- Added more options for interrupts
42-
- Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans"
43-
- revision: "0.5"
44-
date: 2024-06-03
45-
changes:
46-
- Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation
47-
- Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
48-
these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet).
49-
- Added table showing mapping of MC versions to associated RISC-V specifications
50-
- revision: "0.4"
51-
date: 2024-06-03
52-
changes:
53-
- Added M-mode instruction requirements
54-
- Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
55-
- Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
56-
- revision: "0.3"
57-
date: 2024-05-25
58-
changes:
59-
- Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
60-
- revision: "0.2"
61-
date: 2024-05-20
62-
changes:
63-
- Very early draft
64-
- revision: "0.1"
65-
date: 2024-05-16
66-
changes:
67-
- Initial version
18+
revision_history:
19+
- revision: "0.7.0"
20+
date: 2024-07-29
21+
changes:
22+
- First version after moving non-microcontroller content in this document to a new document
23+
called "RISC-V CRDs (Certification Requirement Documents)"
24+
- Change MC100 Unpriv ISA spec from
25+
"https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf[riscv-spec-v2.1], May 31,
26+
2016" to https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC since the
27+
former isn't ratified by the latter is the oldest ratified version.
28+
- Added requirements for WFI instruction
29+
- Added requirements related to msip memory-mapped register
30+
- revision: "0.6.0"
31+
date: 2024-07-11
32+
changes:
33+
- Supporting multiple MC versions to support customers wanting to certify existing microcontrollers not using the latest version of ratified standards.
34+
- Changed versioning scheme to use major.minor.patch instead of 3-digit major & minor.
35+
- Added a table showing the mapping from MC version to ISA manuals.
36+
- Reluctantly made interrupts OUT OF SCOPE for MC100 since only the CLINT interrupt controller
37+
was ratified at that time and isn't anticipated to be the interrupt controller used by MC100 implementations.
38+
- Clarified MANDATORY behaviors for mie and mip CSRs
39+
- Removed canonical discovery recipe because the OPT-* options directly inform the certification
40+
tests and certification reference model of the status of the various options. Also, canonical
41+
discovery recipes (e.g., probing for CLIC) violate the certification approach of avoiding writing
42+
potentially illegal values to CSR fields.
43+
- Added more options for interrupts
44+
- Moved non-microcontroller content in this document to a new document called "RISC-V Certification Plans"
45+
- revision: "0.5.0"
46+
date: 2024-06-03
47+
changes:
48+
- Renamed to "RISC-V Microcontroller Certification Plan" based on Jason's recommendation
49+
- Added mvendorid, marchid, mimpid, and mhardid read-only priv CSRs because Allen pointed out
50+
these are mandatory in M-mode v1.13 (probably older versions too, haven't looked yet).
51+
- Added table showing mapping of MC versions to associated RISC-V specifications
52+
- revision: "0.4.0"
53+
date: 2024-06-03
54+
changes:
55+
- Added M-mode instruction requirements
56+
- Made Zicntr MANDATORY due to very low cost for implementations to support (in the spirit of minimizing options).
57+
- Removed OPT-CNTR-PREC since minstret and mcycle must be a full 64 bits to be standard-compliant.
58+
- revision: "0.3.0"
59+
date: 2024-05-25
60+
changes:
61+
- Includes Zicntr as OPTIONAL and then has only 32-bit counters for instret and cycle.
62+
- revision: "0.2.0"
63+
date: 2024-05-20
64+
changes:
65+
- Very early draft
66+
- revision: "0.1.0"
67+
date: 2024-05-16
68+
changes:
69+
- Initial version
6870

69-
description: |
70-
MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support:
71+
description: |
72+
MC100 can be though of as minimal 32-bit RISC-V processors with M-mode support:
7173
72-
* The Unprivileged ISA is RV32I with a few extensions suitable for a basic microcontroller
73-
* The M-mode features are those listed as mandatory in the associated RISC-V Privileged ISA manual
74+
* The Unprivileged ISA is RV32I with a few extensions suitable for a basic microcontroller
75+
* The M-mode features are those listed as mandatory in the associated RISC-V Privileged ISA manual
7476
75-
Key features not included in MC100 (i.e., OUT OF SCOPE):
77+
Key features not included in MC100 (i.e., OUT OF SCOPE):
7678
77-
* Interrupt Controller (e.g., CLIC, CLINT, PLIC)
78-
* Features for modes other than M-mode
79-
* PMP
80-
* Debug & trace (TBD)
79+
* Interrupt Controller (e.g., CLIC, CLINT, PLIC)
80+
* Features for modes other than M-mode
81+
* PMP
82+
* Debug & trace (TBD)
8183
82-
# Specification versions
83-
tsc_profile: null # None for MC100
84-
unpriv_isa_manual_revision: "20191213"
85-
priv_isa_manual_revision: "20190608-Priv-MSU-Ratified"
86-
debug_manual_revision: "0.13.2"
84+
# Specification versions
85+
tsc_profile: null # None for MC100
86+
unpriv_isa_manual_revision: "20191213"
87+
priv_isa_manual_revision: "20190608-Priv-MSU-Ratified"
88+
debug_manual_revision: "0.13.2"
8789

8890
# XXX - Remove version information since specifying priv/unpriv ISA manual should imply this.
89-
extensions:
90-
I:
91-
version: "~> 2.1"
92-
presence: mandatory
93-
C:
94-
version: "~> 2.2"
95-
presence: mandatory
96-
M:
97-
version: "~> 2.0"
98-
presence: mandatory
99-
Zicsr:
100-
version: "~> 2.0"
101-
presence: mandatory
102-
Zicntr:
103-
version: "~> 2.0"
104-
presence: mandatory
105-
parameters:
106-
TIME_CSR_IMPLEMENTED: {} # Unconstrained
107-
Sm:
108-
version: "~> 1.11.0"
109-
presence: mandatory
110-
parameters:
111-
MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
112-
MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained
113-
ARCH_ID: {} # Unconstrained
114-
IMP_ID: {} # Unconstrained
115-
VENDOR_ID_BANK: {} # Unconstrained
116-
VENDOR_ID_OFFSET: {} # Unconstrained
117-
MISA_CSR_IMPLEMENTED: {} # Unconstrained
118-
MTVAL_WIDTH: {} # Unconstrained
119-
MTVEC_MODES: {} # Unconstrained
120-
PHYS_ADDR_WIDTH: {} # Unconstrained
121-
MISALIGNED_LDST: {} # Unconstrained
122-
MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained
123-
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained
124-
MISALIGNED_SPLIT_STRATEGY:
125-
schema:
126-
const: by_byte
127-
PRECISE_SYNCHRONOUS_EXCEPTIONS:
128-
schema:
129-
const: true
130-
TRAP_ON_ECALL_FROM_M:
131-
schema:
132-
const: true
133-
TRAP_ON_EBREAK:
134-
schema:
135-
const: true
136-
M_MODE_ENDIANESS:
137-
schema:
138-
const: little
139-
XLEN:
140-
schema:
141-
const: 32
91+
extensions:
92+
I:
93+
version: "~> 2.1"
94+
presence: mandatory
95+
C:
96+
version: "~> 2.2"
97+
presence: mandatory
98+
M:
99+
version: "~> 2.0"
100+
presence: mandatory
101+
Zicsr:
102+
version: "~> 2.0"
103+
presence: mandatory
104+
Zicntr:
105+
version: "~> 2.0"
106+
presence: mandatory
107+
parameters:
108+
TIME_CSR_IMPLEMENTED: {} # Unconstrained
109+
Sm:
110+
version: "~> 1.11.0"
111+
presence: mandatory
112+
parameters:
113+
MTVEC_BASE_ALIGNMENT_DIRECT: {} # Unconstrained
114+
MTVEC_BASE_ALIGNMENT_VECTORED: {} # Unconstrained
115+
ARCH_ID: {} # Unconstrained
116+
IMP_ID: {} # Unconstrained
117+
VENDOR_ID_BANK: {} # Unconstrained
118+
VENDOR_ID_OFFSET: {} # Unconstrained
119+
MISA_CSR_IMPLEMENTED: {} # Unconstrained
120+
MTVAL_WIDTH: {} # Unconstrained
121+
MTVEC_MODES: {} # Unconstrained
122+
PHYS_ADDR_WIDTH: {} # Unconstrained
123+
MISALIGNED_LDST: {} # Unconstrained
124+
MISALIGNED_LDST_EXCEPTION_PRIORITY : {} # Unconstrained
125+
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: {} # Unconstrained
126+
MISALIGNED_SPLIT_STRATEGY:
127+
schema:
128+
const: by_byte
129+
PRECISE_SYNCHRONOUS_EXCEPTIONS:
130+
schema:
131+
const: true
132+
TRAP_ON_ECALL_FROM_M:
133+
schema:
134+
const: true
135+
TRAP_ON_EBREAK:
136+
schema:
137+
const: true
138+
M_MODE_ENDIANESS:
139+
schema:
140+
const: little
141+
XLEN:
142+
schema:
143+
const: 32

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