Smrnmi/Smdbltrp extensions fixes (#472)

* Smrnmi/Smdbltrp extensions fixes

Signed-off-by: Albert Yosher <[email protected]>

* Smrnmi extension: should be priviledged as describe in vol.2 section 8.

Signed-off-by: Albert Yosher <[email protected]>

* Smrnmi extension: Fix mnepc CSR logic and reset value for mnepc and mnscratch CSRs

Signed-off-by: Albert Yosher <[email protected]>

---------

Signed-off-by: Albert Yosher <[email protected]>

Author: ayosher

arch/csr/Smrnmi/mnepc.yaml

@@ -0,0 +1,48 @@
+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: mnepc
+long_name: Machine Exception Program Counter
+address: 0x741
+priv_mode: M
+length: MXLEN
+description: |
+  Written with the PC of an instruction on an exception or interrupt taken in M-mode.
+
+  Also controls where the hart jumps on an exception return from M-mode.
+definedBy: Sm
+fields:
+  PC:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    description: |
+      When a NMI / double trap is taken into M-mode, `mnepc.PC` is written with the virtual address of the
+      instruction that was interrupted or that encountered the exception.
+      Otherwise, `mnepc.PC` is never written by the implementation, though it may be explicitly written
+      by software.
+
+      On an exception return from M-mode NMI / double trap (from the MNRET instruction),
+      control transfers to the virtual address read out of `mnepc.PC`.
+
+      [when,"ext?(:C)"]
+      Because PCs are always halfword-aligned, bit 0 of `mnepc.PC` is always
+      read-only 0.
+
+      [when,"!ext?(:C)"]
+      Because PCs are always word-aligned, bits 1:0 of `mnepc.PC` are always
+      read-only 0.
+
+      [when,"ext?(:C) && MUTABLE_MISA_C == true"]
+      When `misa.C` is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
+      may be visible on the next read with `misa.C` is set.
+    type: RW-RH
+    sw_write(csr_value): |
+      return csr_value.PC & ~64'b1;
+    reset_value: UNDEFINED_LEGAL
+sw_read(): |
+  if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
+    return CSR[mnepc].PC & ~64'b1;
+  } else {
+    return CSR[mnepc].PC & ~64'b11;
+  }

arch/csr/Smrnmi/mnscratch.yaml

@@ -0,0 +1,18 @@
+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: mnscratch
+long_name: Machine Scratch Register
+address: 0x740
+priv_mode: M
+length: MXLEN
+description: Scratch register for software use in NMI / double trap. Bits are not interpreted by hardware.
+definedBy: Smrnmi
+fields:
+  SCRATCH:
+    location_rv32: 31-0
+    location_rv64: 63-0
+    description: Scratch value
+    type: RW
+    reset_value: UNDEFINED_LEGAL

arch/csr/Smrnmi/mnstatus.yaml

@@ -0,0 +1,87 @@
+# yaml-language-server: $schema=../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: mnstatus
+long_name: Machine NMI Status
+address: 0x744
+priv_mode: M
+
+# length is MXLEN-bit
+length: MXLEN
+description: The mnstatus register tracks and controls the hart's current NMI operating state.
+definedBy: Smrnmi
+fields:
+  MNPP:
+    location: 12-11
+    description: |
+      M-mode NMI Previous Privilege.
+
+      Written by hardware in two cases:
+
+      * Written with the prior nominal privilege level when entering M-mode NMI from an exception/interrupt.
+      * Written with 0 when executing an `mnret` instruction to return from a double exception / NMI in M-mode.
+
+      Can also be written by software without immediate side-effect.
+
+      Affects execution in two cases:
+
+      * On a return from a double exception / NMI from M-mode, the machine will
+      enter the privilege level stored in MNPP before clearing the field.
+      * When `mnstatus.MNPRV` is set, loads and stores behave as if the current privilege level were MNPP.
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    sw_write(csr_value): |
+      if (csr_value.MNPP == 2'b01 && !implemented?(ExtensionName::S)) {
+        return UNDEFINED_LEGAL_DETERMINISTIC;
+      } else if (csr_value.MNPP == 2'b00 && !implemented?(ExtensionName::U)) {
+        return UNDEFINED_LEGAL_DETERMINISTIC;
+      } else if (csr_value.MNPP == 2'b10) {
+        # never a valid value
+        return UNDEFINED_LEGAL_DETERMINISTIC;
+      } else {
+        return csr_value.MNPP;
+      }
+    legal?(csr_value): |
+      if (csr_value.MNPP == 2'b01 && !implemented?(ExtensionName::S)) {
+        return false;
+      } else if (csr_value.MNPP == 2'b00 && !implemented?(ExtensionName::U)) {
+        return false;
+      } else if (csr_value.MNPP == 2'b10) {
+        # never a valid value
+        return false;
+      } else {
+        return true;
+      }
+  MNPV:
+    location: 7
+    description: |
+      *Machine Previous NMI Virtualization mode*
+
+      Written with the prior virtualization mode when entering M-mode from an exception/interrupt.
+      When returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0.
+      Can also be written by software.
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
+    definedBy: H
+  NMIE:
+    location: 3
+    description: |
+      *M-mode NMI Enable*
+
+      Written by hardware in two cases:
+
+      * Written with the value 0 when entering M-mode NMI.
+      * Written with the value 0 when entering M-mode double trap.
+
+      Written by software in one case only:
+
+      * The NMIE is 0 on reset for boot code to initialize system to service NMIs. Once SW writes NMIE to 1, it cannot be changed anymore by SW.
+
+      Affects execution by:
+
+      * When 0, all non-maskable interrupts and exceptions are disabled when the current privilege level is M.
+      * When 1, NMI or double trap is possible.
+
+    type: RW-H
+    reset_value: 0

arch/csr/mstatus.yaml

@@ -46,6 +46,19 @@ fields:
         return UNDEFINED_LEGAL;
       }
 
+  MDT:
+    location: 42
+    base: 64
+    description: |
+      *Machine Disable Trap*
+
+      Written to 1 when entering M-mode from an exception/interrupt.
+      When returning via an MRET instruction, the bit is written to 0.
+      On reset in set to 1, and software should write it to 0 when boot sequence is done.
+      When mstatus.MDT=1, direct write by CSR instruction cannot set mstatus.MIE to 1, if not written together.
+    definedBy: Smdbltrp
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
   MPV:
     location: 39
     base: 64

arch/csr/mstatush.yaml

@@ -13,6 +13,18 @@ definedBy:
   name: Sm
   version: ">= 1.12"
 fields:
+  MDT:
+    location: 10
+    description: |
+      *Machine Disable Trap*
+
+      Written to 1 when entering M-mode from an exception/interrupt.
+      When returning via an MRET instruction, the bit is written to 0.
+      On reset in set to 1, and software should write it to 0 when boot sequence is done.
+      When mstatush.MDT=1, direct write by CSR instruction cannot set mstatus.MIE to 1.
+    definedBy: Smdbltrp
+    type: RW-H
+    reset_value: UNDEFINED_LEGAL
   MPV:
     location: 7
     description: |

arch/ext/Smrnmi.yaml

@@ -14,7 +14,7 @@ description: |
   The `Smrnmi` extension adds support for resumable non-maskable interrupts (RNMIs) to RISC-V.
   The extension adds four new CSRs (`mnepc`, `mncause`, `mnstatus`, and `mnscratch`) to hold the
   interrupted state, and one new instruction, `mnret`, to resume from the RNMI handler.
-type: unprivileged
+type: privileged
 versions:
   - version: "1.0.0"
     state: ratified

arch/inst/Smrnmi/mnret.yaml

@@ -18,3 +18,15 @@ access:
   vu: always
 data_independent_timing: false
 operation(): |
+  if (implemented?(ExtensionName::S) && CSR[mstatus].MPP != 2'b11) {
+    CSR[mstatus].MPRV = 0;
+  }
+  if (CSR[mnstatus].MNPP == 2'b00) {
+    set_mode(PrivilegeMode::U);
+  } else if (CSR[mnstatus].MNPP == 2'b01) {
+    set_mode(PrivilegeMode::S);
+  } else if (CSR[mnstatus].MNPP == 2'b11) {
+    set_mode(PrivilegeMode::M);
+  }
+  CSR[mnstatus].MNPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11;
+  $pc = $bits(CSR[mnepc]);