adress dhower's feedback

Author: jmawet

spec/std/isa/csr/V/vcsr.yaml

@@ -18,13 +18,17 @@ fields:
     location: 2-1
     description: See vxrm.
     type: RW-RH
+    alias: vxrm.VALUE[1:0]
     sw_write(csr_value): |
+      CSR[vxrm].VALUE = csr_value.VXRM;
       return csr_value.VXRM;
     reset_value: UNDEFINED_LEGAL
   VXSAT:
     location: 0
     description: See vxsat.
     type: RW-RH
+    alias: vxsat.VALUE[0]
     sw_write(csr_value): |
+      CSR[vxsat].VALUE = csr_value.VXSAT;
       return csr_value.VXSAT;
     reset_value: UNDEFINED_LEGAL

spec/std/isa/csr/V/vl.yaml

@@ -27,4 +27,5 @@ fields:
       and supporting SEW=8 would need at least six bits in vl to hold the values 0-32
       (VLEN=32, with LMUL=8 and SEW=8, yields VLMAX=32).
     type: RO-H
-    reset_value: 0
+    reset_value(): |
+      return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;

spec/std/isa/csr/V/vstart.yaml

@@ -69,6 +69,11 @@ fields:
       supported vstart element position. Alternatively, migration events can be constrained to
       only occur at mutually supported vstart locations.
     sw_write(csr_value): |
-      return csr_value.VALUE & (VLEN - 1);
+      XReg newval = csr_value.VALUE & (VLEN - 1);
+      if (newval != csr_value.VALUE) {
+        return UNDEFINED_LEGAL;
+      } else {
+        return newval;
+      }
     type: RW-RH
     reset_value: UNDEFINED_LEGAL

spec/std/isa/csr/V/vtype.yaml

@@ -32,7 +32,8 @@ fields:
 
       It is recommended that at reset, vill is set.
     type: RO-H
-    reset_value: 1
+    reset_value(): |
+      return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 1 : UNDEFINED_LEGAL;
   VMA:
     location: 7
     description: |
@@ -50,7 +51,8 @@ fields:
 
       It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
     type: RO-H
-    reset_value: 0
+    reset_value(): |
+      return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;
   VTA:
     location: 6
     description: |
@@ -68,7 +70,8 @@ fields:
 
       It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
     type: RO-H
-    reset_value: 0
+    reset_value(): |
+      return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;
   VSEW:
     location: 5-3
     description: |
@@ -86,7 +89,8 @@ fields:
 
       It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
     type: RO-H
-    reset_value: 0
+    reset_value(): |
+      return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;
   VLMUL:
     location: 2-0
     description: |
@@ -115,4 +119,5 @@ fields:
 
       It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
     type: RO-H
-    reset_value: 0
+    reset_value(): |
+      return (FOLLOW_VTYPE_RESET_RECOMMENDATION)? 0 : UNDEFINED_LEGAL;

spec/std/isa/csr/V/vxrm.yaml

@@ -17,7 +17,6 @@ sw_read(): |
   return CSR[vcsr].VXRM;
 fields:
   VALUE:
-    alias: vcsr.VXRM
     location_rv32: 31-0
     location_rv64: 63-0
     description: |

spec/std/isa/ext/V.yaml

@@ -56,13 +56,27 @@ params:
     schema:
       type: string
       enum: ["ceil(AVL/2)", "VLMAX", "custom"]
+  FOLLOW_VTYPE_RESET_RECOMMENDATION:
+    description: |
+      The spec recommends - but does not require - that on reset, vill is set, and remaining bits in vtype and vl are set to 0.
+      If this parameter is set to true, the CSR resets will follow this recommandation. If it is false, the resets will be "UNDEFINED_LEGAL".
+    schema:
+      type: boolean
   VLEN:
     description: |
-      The number of bits in a single vector register. VLEN >= ELEN, which must be a power of 2, and must be no greater than 2^16.
+      The number of bits in a single vector register.
     schema:
       type: integer
+#    requirements:
+#      idl(): |
+#        -> (VLEN >= ELEN) && (VLEN <='h10000) && (popcount(VLEN) == 1);
+#      reason: VLEN >= ELEN, which must be a power of 2, and must be no greater than 2^16.
   ELEN:
     description: |
-      The maximum size in bits of a vector element that any operation can produce or consume, ELEN >= 8, which must be a power of 2.
+      The maximum size in bits of a vector element that any operation can produce or consume.
     schema:
       type: integer
+#    requirements:
+#      idl(): |
+#        -> (ELEN >='h8) && (popcount(ELEN) == 1);
+#      reason: ELEN >= 8, which must be a power of 2.

spec/std/isa/inst/V/vsetivli.yaml

@@ -28,7 +28,7 @@ data_independent_timing: false
 operation(): |
   VectorState state = vector_state();
   XReg vlen = VLEN;
-  XReg vlmax = (vlen << state.log2_multiplier) >> (3 + state.vsew);
+  XReg vlmax = (vlen << state.log2_multiplier) >> (3 + state.sew);
   XReg AVL = uimm;
   XReg CEIL_AVL_OVER_TWO = (AVL + 1) / 2;
 

spec/std/isa/inst/V/vsetvl.yaml

@@ -28,7 +28,7 @@ data_independent_timing: false
 operation(): |
   VectorState state = vector_state();
   XReg vlen = VLEN;
-  XReg vlmax = (vlen << state.log2_multiplier) >> (3 + state.vsew);
+  XReg vlmax = (vlen << state.log2_multiplier) >> (3 + state.sew);
   XReg AVL = xs1;
   XReg CEIL_AVL_OVER_TWO = (AVL + 1) / 2;
 

spec/std/isa/inst/V/vsetvli.yaml

@@ -28,7 +28,7 @@ data_independent_timing: false
 operation(): |
   VectorState state = vector_state();
   XReg vlen = VLEN;
-  XReg vlmax = (vlen << state.log2_multiplier) >> (3 + state.vsew);
+  XReg vlmax = (vlen << state.log2_multiplier) >> (3 + state.sew);
   XReg AVL = xs1;
   XReg CEIL_AVL_OVER_TWO = (AVL + 1) / 2;
 

spec/std/isa/isa/vec.idl

@@ -12,18 +12,15 @@
 #   - integer widening arith ()
 
 # the vector register file
-Bits<VLEN> v[32] = [0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0,
-                    0, 0, 0, 0, 0, 0, 0, 0];
+Bits<VLEN> v[32];
 
 enum VectorLmulType {
   Divide
   Multiply
 }
 
 struct VectorState {
-  Bits<7> vsew;
+  Bits<7> sew;
   VectorLmulType lmul_type;
   Bits<2> log2_multiplier;
 }
@@ -36,7 +33,7 @@ function vector_state {
   body {
     VectorState state;
 
-    state.vsew = 7'b1 << (3 + CSR[vtype].VSEW);
+    state.sew = 7'b1 << (3 + CSR[vtype].VSEW);
     Bits<3> vlmul = CSR[vtype].VLMUL;
     state.lmul_type = CSR[vtype].VLMUL[2] == 1'b1 ? VectorLmulType::Divide : VectorLmulType::Multiply;
     state.log2_multiplier = CSR[vtype].VLMUL[1:0];