Skip to content

Commit 8ce8d85

Browse files
author
Derek Hower
committed
Add fp.idl, fix FP operation()s from merge
1 parent 0a28964 commit 8ce8d85

25 files changed

+568
-153
lines changed

‎arch/csr/fcsr.yaml‎ renamed to ‎arch/csr/F/fcsr.yaml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
# yaml-language-server: $schema=../../schemas/csr_schema.json
1+
# yaml-language-server: $schema=../../../schemas/csr_schema.json
22

33
fcsr:
44
long_name: Floating-point control and status register (`frm` + `fflags`)
@@ -93,7 +93,7 @@ fcsr:
9393
length: 32
9494
definedBy: F
9595
fields:
96-
RMODE:
96+
FRM:
9797
location: 7-5
9898
description: |
9999
Rounding modes are encoded as follows:
@@ -179,4 +179,4 @@ fcsr:
179179
Set by hardware when a floating point operation is inexact and stays set until explicitly
180180
cleared by software.
181181
type: RW-H
182-
reset_value: UNDEFINED_LEGAL
182+
reset_value: UNDEFINED_LEGAL

‎arch/ext/F.yaml‎

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -239,6 +239,20 @@ F:
239239
Indicates whether or not the `F` extension can be disabled with the `misa.F` bit.
240240
schema:
241241
type: boolean
242+
HW_MSTATUS_FS_DIRTY_UPDATE:
243+
description: |
244+
Indicates whether or not hardware will write to `mstatus.FS`
245+
246+
Values are:
247+
[separator="!"]
248+
!===
249+
h! none ! Hardware never writes `mstatus.FS`
250+
h! precise ! Hardware writes `mstatus.FS` to the Dirty (3) state precisely when F registers are modified
251+
h! imprecise ! Hardware writes `mstatus.FS` imprecisely. This will result in a call to unpredictable() on any attempt to read `mstatus` or write FP state.
252+
!===
253+
schema:
254+
type: string
255+
enum: ["none", "precise", "imprecise"]
242256
MSTATUS_FS_LEGAL_VALUES:
243257
description: |
244258
The set of values that mstatus.FS will accept from a software write.
@@ -251,4 +265,7 @@ F:
251265
uniqueItems: true
252266
also_defined_in: S
253267
extra_validation: |
254-
assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F)
268+
assert MSTATUS_FS_LEGAL_VALUES.include?(0) && MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F)
269+
270+
# if HW is writing FS, then Dirty (3) better be a supported value
271+
assert MSTATUS_FS_LEGAL_VALUES.include?(3) if ext?(:F) && (HW_MSTATUS_FS_DIRTY_UPDATE != "none")

‎arch/inst/F/fclass.s.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ fclass.s:
4545
vu: always
4646
data_independent_timing: false
4747
operation(): |
48-
check_f_ok();
48+
check_f_ok($encoding);
4949
5050
Bits<32> sp_value = f[fs1][31:0];
5151

‎arch/inst/F/fcvt.s.w.yaml‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ fcvt.s.w:
2222
location: 19-15
2323
- name: rm
2424
location: 14-12
25-
- name: rd
25+
- name: fd
2626
location: 11-7
2727
access:
2828
s: always
@@ -31,15 +31,15 @@ fcvt.s.w:
3131
vu: always
3232
data_independent_timing: false
3333
operation(): |
34-
check_f_ok();
34+
check_f_ok($encoding);
3535
3636
Bits<32> int_value = X[rs1];
3737
3838
Bits<1> sign = int_value[31];
3939
40-
RoundingMode rouding_mode = rm_to_mode(rm, $encoding);
40+
RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
4141
42-
if (! (int_value & 32'h7fff_ffff)) {
42+
if ((int_value & 32'h7fff_ffff) == 0) {
4343
X[fd] = (sign == 1) ? packToF32UI(1, 0x9E, 0) : 0;
4444
} else {
4545
Bits<32> absA = (sign == 1) ? -int_value : int_value;

‎arch/inst/F/fcvt.w.s.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ fcvt.w.s:
5151
vu: always
5252
data_independent_timing: true
5353
operation(): |
54-
check_f_ok();
54+
check_f_ok($encoding);
5555
5656
Bits<32> sp_value = f[fs1][31:0];
5757

‎arch/inst/F/feq.s.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ feq.s:
2727
vu: always
2828
data_independent_timing: true
2929
operation(): |
30-
check_f_ok();
30+
check_f_ok($encoding);
3131
3232
Bits<32> sp_value_a = f[fs1][31:0];
3333
Bits<32> sp_value_b = f[fs1][31:0];

‎arch/inst/F/fle.s.yaml‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,13 @@ fle.s:
1111
Positive zero and negative zero are considered equal.
1212
1313
definedBy: F
14-
assembly: xd, xs1, xs2
14+
assembly: xd, fs1, fs2
1515
encoding:
1616
match: 1010000----------000-----1010011
1717
variables:
18-
- name: rs2
18+
- name: fs2
1919
location: 24-20
20-
- name: rs1
20+
- name: fs1
2121
location: 19-15
2222
- name: rd
2323
location: 11-7
@@ -28,10 +28,10 @@ fle.s:
2828
vu: always
2929
data_independent_timing: true
3030
operation(): |
31-
check_f_ok();
31+
check_f_ok($encoding);
3232
3333
Bits<32> sp_value_a = f[fs1][31:0];
34-
Bits<32> sp_value_b = f[fs1][31:0];
34+
Bits<32> sp_value_b = f[fs2][31:0];
3535
3636
if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
3737
if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {

‎arch/inst/F/flt.s.yaml‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,9 @@ flt.s:
1313
encoding:
1414
match: 1010000----------001-----1010011
1515
variables:
16-
- name: rs2
16+
- name: fs2
1717
location: 24-20
18-
- name: rs1
18+
- name: fs1
1919
location: 19-15
2020
- name: rd
2121
location: 11-7
@@ -26,10 +26,10 @@ flt.s:
2626
vu: always
2727
data_independent_timing: true
2828
operation(): |
29-
check_f_ok();
29+
check_f_ok($encoding);
3030
3131
Bits<32> sp_value_a = f[fs1][31:0];
32-
Bits<32> sp_value_b = f[fs1][31:0];
32+
Bits<32> sp_value_b = f[fs2][31:0];
3333
3434
if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
3535
set_fp_flag(FpFlag::NV);

‎arch/inst/F/flw.yaml‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3,20 +3,20 @@
33
flw:
44
long_name: Single-precision floating-point load
55
description: |
6-
The `flw` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _rd_.
6+
The `flw` instruction loads a single-precision floating-point value from memory at address _rs1_ + _imm_ into floating-point register _fd_.
77
88
`flw` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.
99
1010
definedBy: F
11-
assembly: xd, xs1, imm
11+
assembly: fd, xs1, imm
1212
encoding:
1313
match: -----------------010-----0000111
1414
variables:
1515
- name: imm
1616
location: 31-20
1717
- name: rs1
1818
location: 19-15
19-
- name: rd
19+
- name: fd
2020
location: 11-7
2121
access:
2222
s: always
@@ -25,14 +25,14 @@ flw:
2525
vu: always
2626
data_independent_timing: true
2727
operation(): |
28-
check_f_ok();
28+
check_f_ok($encoding);
2929
3030
XReg virtual_address = X[rs1] + $signed(imm);
3131
32-
Bits<32> sp_value = read_memory<32>(virtual_address);
32+
Bits<32> sp_value = read_memory<32>(virtual_address, $encoding);
3333
3434
if (implemented?(ExtensionName::D)) {
35-
f[fd] = nan_box(sp_value);
35+
f[fd] = nan_box<32, 64>(sp_value);
3636
} else {
3737
f[fd] = sp_value;
3838
}

‎arch/inst/F/fmv.w.x.yaml‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ fmv.w.x:
1414
variables:
1515
- name: rs1
1616
location: 19-15
17-
- name: rd
17+
- name: fd
1818
location: 11-7
1919
access:
2020
s: always
@@ -23,12 +23,12 @@ fmv.w.x:
2323
vu: always
2424
data_independent_timing: true
2525
operation(): |
26-
check_f_ok();
26+
check_f_ok($encoding);
2727
2828
Bits<32> sp_value = X[rs1][31:0];
2929
3030
if (implemented?(ExtensionName::D)) {
31-
f[fd] = nan_box(sp_value);
31+
f[fd] = nan_box<32, 64>(sp_value);
3232
} else {
3333
f[fd] = sp_value;
3434
}

0 commit comments

Comments
 (0)